• State
  • Replies 2 replies
  • Subscribers 47 subscribers
  • Views 39 views
  • Users 0 members are here
Support feedback
Options
Options
Related

DAC80508: STM32U5 SPI update of DAC80508 via DMA and PWM Timer

Frank Braeuer
Prodigy 10 points
Part Number: DAC80508

Tool/software:

I have connected the DAC80508 EVB to a STM32U5 Nucleo testboard. The DAC chip-select (CS) shall be driven from the microcontroller via DMA and a timer (PWM).

I'm sending 4 samples, each a 32bit word. The DAC is by default configured in asynchronous mode.

When updating the DAC from the code via codebase-driven CS, the output of the DAC is updated immediately after the CS goes high.

When driving the CS via a PWM timer, and using DMA for shifting the samples out, on the scope everything looks the same, all timings are far beyond the dataspec limits. However, the DAC does not update the output for the first 3 samples, only after the 4th it's updating the output. It's always the last, even when sending 100 samples.

Pic1: code-driven CS, working correctly, CS=red, CLK=blue, DATA=green, DACout=yellow

Code-driven CS

Pic2: timer driven CS, DMA-driven samples, DAC output not working, , CS=red, CLK=blue, DATA=green, DACout=yellow

Timer/DMA driven CS

My suspicion is that the DAC is not updating the output as long the ST is actively holding the CLK pin. As you can see in the 2nd picture, the blue CLK is held by the microcontroller, only after the last sample is sent out via DMA it seems to release the CLK (little upward tick), and exactly after this the DAC is updating its output. 

When the CS is driven by the code and every sample is sent out separately, the CLK always shows the little upward tick (picture 1), which seems to be the trigger for the DAC to update its output..

I'm looking for an explanation for this behavior, since the DAC datasheet is not giving details in this regard.

  • 0
    TI__Mastermind 42113 points

    Hi Frank, 

    What is the logic level of you SPI? What do you have VIO and VDD connected to on the EVM? Maybe a picture of your entire EVM configuration would be helpful so I understand your setup.

    This should not be the behavior, though I see what you are saying from the screenshots with the DAC output seeming to be tied to the CLK being released by your MCU. The rising edge of CS should be the trigger to the DAC to update the output based on the data shifted in on the last 24 clock cycles. 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    TI__Guru* 97775 points

    Frank,


    Other than Katlynne asking about the VIO level, I did a quick compare of closeups between the two plots (top one good, second one bad). There are some small timing differences, but I didn't see anything that would lead me to think there would be a problem. It looks like the DIN and SCLK are coming in correctly.

    However, I did see quite a bit of noise in the scope shots, which leads me to wonder if there's a blip that's a bit fast to see. If there's a little bit of noise on SCLK, then that noise might be interpreted as an SCLK pulse. This would shift the incoming data and be misinterpreted. One thing to try would be to clean up this noise and hang a 10 to 100pF capacitance off of SCLK and see if it clears up the problem.

    Joseph Wu