TI-JESD204-IP: Pulse Width Errors in Vivado Timing Analysis

mitsuo ono

Prodigy 70 points

Part Number: TI-JESD204-IP
Other Parts Discussed in Thread: ADC09DJ1300

Tool/software:

Hello, experts,

I'm having trouble resolving a pulse width errors in Vivado timing analysis.

(Error screen)

Is the operation of the ADC09DJ1300 and TI-JESD204C-IP guaranteed with this configuration?
Is it even possible to use them with this setup?
If there are any settings I might have overlooked, please advise.

(Settings)

Devices:

ADC09DJ1300

TI-JESD204C-IP Release-v1.10-LATEST

Xilinx Zynq-7000 xa7z030fbv484-1Q

Design Parameters:

Dual Channel mode

Sampling 1.25GSPS

JMODE 9 (8bit,4lanes,8B/10B)

JESD204C Subclass0

LineRate 6.25Gbps

Host PC:

Vivado 2022.1

Win11

(Vivado Tranceiver Wiz)

Thank you.

1 month ago

0 Ameet Bagwe 1 month ago

TI__Intellectual 2410 points

Hi,

The pulse width warning is related to the timing analysis (and target FPGA characteristics) and not the architecture of the JESD IP.

In your case, for a line rate of 6.25Gbps, the clock will be 156.25MHz. However, the timing analysis tool seems to be finding a clock frequency of 260MHz, which is higher than the max rating of 200MHz.

Kindly check the input timing constraint on the GT reference clocks. That could be different from the 195.3125MHz value you have used in the wizard.

Regards,

Ameet

+1 mitsuo ono 1 month ago in reply to Ameet Bagwe

Prodigy 70 points

Hello, Ameet,

Understood. So the Pulse Width Error is unrelated to the JESD-IP architecture.

After revising the reference clock to 390.625MHz, the Pulse Width Error was resolved.

I will confirm with the manufacturer regarding the appropriateness of the settings.

Thank you for your kind advice.

Data converters

Data converters forum

TI-JESD204-IP: Pulse Width Errors in Vivado Timing Analysis