TI-JESD204-IP: Pulse Width Errors in Vivado Timing Analysis

Tool/software:

Hello, experts,

I'm having trouble resolving a pulse width errors in Vivado timing analysis.

(Error screen)

Is the operation of the ADC09DJ1300 and TI-JESD204C-IP guaranteed with this configuration?
Is it even possible to use them with this setup?
If there are any settings I might have overlooked, please advise.

(Settings)

Devices:

 ADC09DJ1300

 TI-JESD204C-IP Release-v1.10-LATEST

 Xilinx Zynq-7000 xa7z030fbv484-1Q

Design Parameters:

 Dual Channel mode

 Sampling 1.25GSPS

 JMODE 9 (8bit,4lanes,8B/10B)

 JESD204C Subclass0

 LineRate 6.25Gbps

Host PC:

 Vivado 2022.1

 Win11

(Vivado Tranceiver Wiz)

     

Thank you.