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ADS7038H: SPI Timing w.r.t. tCONV

Florian Holzner
Prodigy 10 points

Part Number: ADS7038H
Other Parts Discussed in Thread: ADS7038, TLA2518

Tool/software:

Hi E2E Team,

I have a question regarding the SPI timing with respect to tCONV. Datasheet SBAS979C chapters 6.6, 6.7 and 6.8 don't show any timing requirements between tCONV and SCLK. Only a timing requirements between CS and SCLK are shown, e.g. tSU_CSCK. This would mean that SCLK could already start before tCONV is complete (if CS goes low early enough). Is that reasonable?

The table in chapter 6.6 shows two QUIET time parameter (tQT_ACQ and tD_CNVCAP), that figure in chapter 6.8 shows only one (tQUIET). What is the other QUIET parameter about?

Thanks,

  Florian

  • 0
    TI__Mastermind 21330 points

    Hi Florian,

    Normally, conversion time begins with the rising edge of ~CS. It is controlled with an internal oscillator, and takes a maximum of 467ns on the ADS7038H. Therefore, it is recommended to keep the ~CS high greater than or equal to the maximum tconv time to avoid any issues in completing the conversion.

    The ~CS high time requirement is implicit due to the tconv timing, but it might help to make a note on it in the datasheet.

    Regards,
    Joel

  • 0 in reply to Joel Meraz
    Prodigy 10 points

    Hi Joel,

    Thanks for your response. I have two respective questions:

    • The datasheet explicitely defines the minimum pulse duration for CS being high with tWH_CSZ = 200ns. This is not consistent with your recommendation. Is this definition wrong then? 
    • If tWH_CSZ would be 467ns then a whole cycle would take at least tCYCLE = 467ns + tSU_CSCK + 11.5 * tCLK + tQUIET = 672,2 ns. This would not be consistent  with the 1500 kSPS specification (which would allow for 666,7 ns only). Is there anything I have misunderstood?

    The background of my question is that I plan to use a timing scheme with limited degree of freedom. For this timing scheme the detailed requirements for tWH_CSZ, tSU_CSCK and tQUIET are important.

    Thanks,
      Florian

  • +1 in reply to Florian Holzner
    TI__Mastermind 21330 points

    Hi Florian,

    Apologies for causing further confusion. Please read the following forum post for the TLA2518, specifically Rahul's responses (also applies for ADS7038/ADS7038H).

     TLA2518: Achieving full throughput with >13.5MHz SPI, Max Conversion Time, tconv = 600ns, and Datasheet Missing Min. Max. Performance Specs 

    It should help clarify the implications around the conversion cycle timing better than I would restate. In short, it will not cause an incorrect result, but performance could become degraded due to digital activity disturbing analog signals.

    I can help clarify remaining questions.

    Regards,
    Joel