ADC12D1600

First a little background on LVDS I/O levels. The standards were developed to allow high speed differential signals to be sent between pieces of equipment, sometimes over cables up to meters in length. In those cases there is the possibility of different GND levels or common mode shifts between the transmit and the receive side. To give the maximum possible common mode capability in those situations it is desired to have the transmitter outputting at a common mode that is exactly in the center of the common mode input range of the receiver.

In the GSPS ADC applications, the transmitter is always located in the same box as the receiver and almost always on the same board. Sometimes the signals may go through a connector or two, but the grounding is usually very good between TX and RX. So we don't have to worry about common mode shifts of any significance.

Since the GSPS ADC devices use a 1.9V supply, it is more challenging to create an LVDS output with a standard 1.2V common mode voltage. So the default mode of operation for these devices has an output common mode voltage of 0.8V. This is lower than the standard 1.2V, but is still well within the common mode range of all LVDS receivers I have reviewed. The Vicm spec for the Kintex 7 (ds182_Kintex_7_Data_Sheet.pdf, Table 8 and Table 9) lists the following: Vicm_min = 0.3V, Vicm_typ = 1.2V, Vicm_max = 1.425V.

Reviewing the Vod levels of the GSPS ADCs, there are two different settings. The lower swing setting provides Vod_typ = 460mVp-p (230mVpk), Vod_min = 230mVp-p (115mVpk) and Vod_max = 630mVp-p (315mVpk). The higher swing setting provides Vod_typ= 630mVp-p (315mVpk), Vod_min = 400mVp-p (200mVpk) and Vod_max = 800mVp-p (400mVpk).  

The bracketed peak values are the ones that are appropriate to compare to the FPGA Vidiff specifications. The Kintex 7 devices have Vidiff_min = 100mV and Vidiff_max = 600mV.

Based on this information the TX and RX common mode and differential levels are completely compatible.