Tool/software:
Hi team
I am testing interoperability of ADC with FPGA for JESD204B subclass1. I started with 4 lane design, where i set ADC for JMODE 2, with F=8, K=4. FxK=32 with LMFC boundary of 8 clock cycles since my interface is 32 bit (32/4=8). For subclass1, i am explicitly setting below ADC registers too.
0x2B0 01
0x29 70
Issue: Time from SYNC DEassertion to first ILA data varies power cycle to power cycle which crosses the LMFC boundary sometimes leading to subclass1 deterministic latency failure. Our LMFC boundary is 8 cycles, so we expect data on every lane to come within 8 cycles. There is no lane skew here , explanation below.
To calculate the time from SYNC deassertion to first ILA data, we run a counter corresponding each lane. count value on each lanes are same in our case.
For example
on first power cycle , count value one each lane = 0x0D, JESD gives dataout on nth LMFC boundary
then on some nth power cycle, count value = 0x15, JESD dataout on n+1th LMFC boundary. This violates the subclass1 requirement.
Please note till my count value= 0x14, JESD gives dataout on nth LMFC boundary. Problem is when count value = 0x15.
Any idea why we see data on FPGA with max difference of 8 cycles power cycle to power cycle voilating LMFC requirement?
Please let me know if i am missing anything.
-trs