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ADC12DJ3200EVM: Not getting deterministic results to prove interoperability of ADC with FPGA for JES204B subclass1

Thakur Rohit Singh
Prodigy 130 points
Part Number: ADC12DJ3200EVM


Tool/software:

Hi team

I am testing interoperability of ADC with FPGA for JESD204B subclass1. I started with 4 lane design, where i set ADC for JMODE 2, with F=8, K=4. FxK=32 with LMFC boundary of 8 clock cycles since my interface is 32 bit (32/4=8). For subclass1, i am explicitly setting below ADC registers too.

0x2B0 01

0x29   70

Issue: Time from SYNC DEassertion to first ILA data varies power cycle to power cycle which crosses the LMFC boundary sometimes leading to subclass1 deterministic latency failure. Our LMFC boundary is 8 cycles, so we expect data on every lane to come within 8 cycles. There is no lane skew here , explanation below.

To calculate the time from SYNC deassertion to first ILA data, we run a counter corresponding each lane. count value on each lanes are same in our case.

For example

on first power cycle , count value one each lane = 0x0D, JESD gives dataout on nth LMFC boundary

then on some nth power cycle, count value = 0x15, JESD dataout on n+1th LMFC boundary. This violates the subclass1 requirement.

Please note till my count value= 0x14, JESD gives dataout on nth LMFC boundary. Problem is when count value = 0x15.

Any idea why we see data on FPGA with max difference of 8 cycles power cycle to power cycle voilating LMFC requirement? 

Please let me know if i am missing anything.

-trs

  • 0
    TI__Intellectual 2410 points

    Hi Rohit,

    I am assuming that the ADC and FPGA are synchronized in terms of LMFC through the SYSREF. One experiment will be to add an offset to the LMFC in the FPGA. If the SYNCn from the FPGA is releasing too close to the LMFC boundary of the ADC, the transition from CGS to ILAS can slip by a multiframe. 

    Regards,

    Ameet 

  • 0
    Prodigy 30 points

    Thanks Ameet for the quick response. 

    We are using F = 8 and K = 4 so LMFC is 32. We have configured 32 bits parallel data width for the SERDES. LMFC rising clock is generated after every 8 clock cycles (for every clock cycle 4 bytes are received -> LMFC/(DATA_WIDTH)/8) = 4). We tried all the possible values of the offset i.e starting from 0 to 7 and we observed CGS to ILAS slip by a multiframe. SYNCN is de-asserted on the next clock cycle of LMFC rising edge i.e with different offset LMFC rising edge is shifted and due to that SYNCN transition is also shifted. 

    We want to try increasing the LMFC from 32 to 64. We are changing the value of K from 4 to 8. With this configuration, it is observed that SYSREF frequency is not reduced and SYSREF is asserted every four clock cycle (same behavior when LMFC = 32) and due to that LMFC counter is also getting reset after every 8 clock cycle. We want to ensure that SYSREF rising edge pulse comes after every 16 clock cycles. Can you please suggest the configuration to reduce SYSREF frequency?

  • 0 in reply to Krupesh Patel
    Prodigy 130 points

    Hi  

    Now we are able to reduce the Sysref by following configuration as highlighted in the below screenshot.

    As mentioned already, our F=8, K=8, with this configuration also we see the same behavior. We tried different LMFC offset to shift the LMFC edge and SYNC but no change in behavior.

    Can you please review our configuration in the ADC EVM GUI and let us know if there is something missing?

    Many thanks for your help.

    -trs

  • 0 in reply to Thakur Rohit Singh
    Prodigy 130 points

    Hi  

    We tried clearing REALIGNED bit of 0x208 register by writing it to 1. 

    before clearing the bit, 0x208 = 7C

    after clearing the bit (by writing 7C), 0x208 = 64

    both ALIGNED, REALIGNED goes zero. is this correct way of testing?

    Also, tried registering the SYNC signal with one f/f but still we see the same behavior, deterministic latency with 1 LMFC difference.

    Any idea/clue as in what is going wrong here, any debugging pointers?

    -trs

  • 0 in reply to Thakur Rohit Singh
    TI__Intellectual 2410 points

    Hi Rohit,

    Kindly send us a block diagram of your FPGA setup (illustrating the clock, SYSREF and data connections). 

    The way to test REALIGNED is to write a '1' only to that bit after it reads '1', but what you have tested is also fine. If the bit doesn't get set again, it means the SYSREF timing is okay.

    Regards,
    Ameet

  • 0 in reply to Ameet Bagwe
    Prodigy 130 points

    Hi  

    Here is our clocking architecture for the FPGA design.

    -trs