ADC3564: Clarification on ADC3564 RegisterConfiguration

Sourav Banerjee

Part Number: ADC3564
Other Parts Discussed in Thread: ADC3664

Tool/software:

Hi,

I’m currently working on a prototype project where I plan to interface the ADC3564 with the ZCU106 FMC. I’ve reviewed the datasheet thoroughly and prepared a configuration script based on the register settings provided.

In this setup, the ADC will be used as a Video ADC, where a pulse-based input from a function generator will be used instead of a direct RF signal from a signal generator.

I intend to configure the chip with a basic setup, and the key requirements are as follows:

Interface: 1-Wire (1 lane per channel)
Resolution: 16-bit
Sampling Rate (Fs): 125 MSPS
Decimation (DCM): x2 (Real Decimation)
FCLK: 62.5 MHz
DCLK/DCLKIN: 500 MHz
NCO: Bypassed / Unused (No mixing)
SYNC: Used for power-down (not synchronization, as only one ADC interface is used per hardware)

I’ve attached the configuration script along with a highlighted and annotated version of the datasheet. I have a few queries and would appreciate your guidance:

Since I’ve selected 16-bit resolution, should the zero-padding be applied to the LSB bits (D0, D1) or the MSB bits (D14, D15)?
Do I need to explicitly program registers 0x39 to 0x60 and 0x61 to 0x88 for the output bit mapper for Channel A and B, respectively?
- If yes, could you please verify whether the attached configuration is correct?
- I came across a note suggesting that the output bit mapping might be handled automatically based on the selected configuration. Could you confirm if manual programming is still required?
Is it feasible to operate the ADC with only one channel and one lane?

Lastly, could someone kindly review the attached script to verify the register configuration sequence and values? I’ve also included the updated datasheet with my highlights and comments for reference.

Thanks in advance for your support!

Best regards,
Sourav

adc3564_datasheet_with_highlights_&_comments.pdf

Fullscreen adc_config_script.txt Download

#=============================================================================
# Video ADC register configuration 
# CSR BASE_ADDR : 0xA000_0000
#=============================================================================
#adc_core_reset
mrd -force 0xA0002004 
mwr -force 0xA0002004 0x0
mrd -force 0xA0002004 

# #################adc register configuration########################
#set this bit for soft_reset (register 0x0) (self clearing bit)
mwr -force 0xA0001008 0x0000
mwr -force 0xA000100C 0x01
mwr -force 0xA0001004 0x1	
after 20
mwr -force 0xA0001008 0x8000
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#output interface mapper (register 0x07)
#1-wire output interface mapper mode
mwr -force 0xA0001008 0x0007
mwr -force 0xA000100C 0x6c
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8007
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#e-fuse loader (register 0x13)
#wait for 1 ms,the set it to 0x0
mwr -force 0xA0001008 0x0013
mwr -force 0xA000100C 0x01
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8013
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 
after 1
mwr -force 0xA0001008 0x0013
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8013
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#power down options (register 0x08)
#global power up(normal mode)
mwr -force 0xA0001008 0x0008
mwr -force 0xA000100C 0x02
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8008
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#global power down (toggle bit[0] of this register)
#mwr -force 0xA0001008 0x0008
#mwr -force 0xA000100C 0x03
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8008
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014 

#power down options for FLCK,DCLK,DA/DB (data lanes)(register 0x09)
#global power up(normal mode) - DA0 & DB0 powered up whereas DA1 & DB1 are powered down(1-lane per channel)
mwr -force 0xA0001008 0x0009
mwr -force 0xA000100C 0x0A
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8009
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#Global power down masking options (register 0x0D)
#For global power down (bit[0] of register 0x08 set to 1),the following interface shall get powerdown:
#(a) sampling clock input buffer 
#(b) reference amplifier
#NOTE: Internal 1.2V bandgap voltage reference will NOT get powered down when global power down is exercised
mwr -force 0xA0001008 0x000D
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x800D
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#SYNC/PDN pin functionlity and REFBUF control (register 0x0E)
#sync/pdn pin shall be used for global power down mode instead of using for synchronization purpose using SPI
#The voltage reference option is selected for External voltage reference with differential sampling clock input buffer 
mwr -force 0xA0001008 0x000E
mwr -force 0xA000100C 0x04
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x800E
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#Differential ended analog input (register 0x11)
mwr -force 0xA0001008 0x0011
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8011
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#Test Patterns (register 0x14/15/16)
#Normal output mode(test pattern output disabled) - default
mwr -force 0xA0001008 0x0014
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8014
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

mwr -force 0xA0001008 0x0015
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8015
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

mwr -force 0xA0001008 0x0016
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8016
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#FCLK configuration (register 0x19)
#FCLK generated from ADC with DDC Bypass mode for 1-wire output
mwr -force 0xA0001008 0x0019
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8019
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#LVDS swing High/low (register 0x1A)
mwr -force 0xA0001008 0x001A
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x801A
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014 

#Output Bit mapper disabled(due to Real Decimation mode being used) & 16-bit resolution set (register 0x1B)
mwr -force 0xA0001008 0x001B
mwr -force 0xA000100C 0x08
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x801B
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#SLVDS output data & DCLK delay (register 0x1E) - default
mwr -force 0xA0001008 0x001E
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x801E
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#FCLK pattern for 1-wire 16 bit resolution (register 0x20/21/22)
mwr -force 0xA0001008 0x0020
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8020
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x0021
mwr -force 0xA000100C 0xF0
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8021
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x0022
mwr -force 0xA000100C 0x0F
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8022
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#DDC enabled and datapath shall include digital features (register 0x24) 
mwr -force 0xA0001008 0x0024
mwr -force 0xA000100C 0x06
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8024
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#DDC Mux enabled, DCM : x2 ,Real decimation, NCO phase as it is (register 0x25) 
mwr -force 0xA0001008 0x0025
mwr -force 0xA000100C 0x98
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8025
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#No Digital Gain added for accounting NCO mixing loss for ADC channel A & B since Real
#decimation is selected and Fs/4 mixing is disabled for both the channels(register 0x26) -default
mwr -force 0xA0001008 0x0026
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8026
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#Output order of I & Q data is not inverted/swapped of channel A (register 0x27) -default
mwr -force 0xA0001008 0x0027
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8027
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#NCO configuration FTW registers (unused) of channel A (register 0x2A/2B/2C/2D) -default
mwr -force 0xA0001008 0x002A
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x802A
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x002B
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x802B
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x002C
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x802C
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x002D
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x802D
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#Output order of I & Q data is not inverted/swapped of channel B (register 0x2E) -default
mwr -force 0xA0001008 0x002E
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x802E
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#NCO configuration FTW registers (unused) of channel B (register 0x31/32/33/34) -default
mwr -force 0xA0001008 0x0031
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8031
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x0032
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8032
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x0033
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8033
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

mwr -force 0xA0001008 0x0034
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8034
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#Output Bit mapper for channel DA0 (1-wire 16 bit resolution mode) -optional (register 0x39 to 0x60)
#mwr -force 0xA0001008 0x004C
#mwr -force 0xA000100C 0x46
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x804C
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x004B
#mwr -force 0xA000100C 0x47
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x804B
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x004A
#mwr -force 0xA000100C 0x4C
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x804A
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0049
#mwr -force 0xA000100C 0x4D
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8049
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0048
#mwr -force 0xA000100C 0x4E
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8048
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0047
#mwr -force 0xA000100C 0x4F
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8047
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0046
#mwr -force 0xA000100C 0x54
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8046
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0045
#mwr -force 0xA000100C 0x55
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8045
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0044
#mwr -force 0xA000100C 0x56
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8044
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0043
#mwr -force 0xA000100C 0x57
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8043
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0042
#mwr -force 0xA000100C 0x5C
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8042
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0041
#mwr -force 0xA000100C 0x5D
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8041
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0040
#mwr -force 0xA000100C 0x5E
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8040
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x003F
#mwr -force 0xA000100C 0x5F
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x803F
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x003E
#mwr -force 0xA000100C 0x64
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x803E
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x003D
#mwr -force 0xA000100C 0x65
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x803D
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014

#Output Bit mapper for channel DB0 (1-wire 16 bit resolution mode) -optional (register 0x61 to 0x88)
#mwr -force 0xA0001008 0x0074
#mwr -force 0xA000100C 0x42
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8074
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0073
#mwr -force 0xA000100C 0x43
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8073
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0072
#mwr -force 0xA000100C 0x48
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8072
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0071
#mwr -force 0xA000100C 0x49
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8071
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0070
#mwr -force 0xA000100C 0x4A
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8070
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x006F
#mwr -force 0xA000100C 0x4B
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x806F
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x006E
#mwr -force 0xA000100C 0x50
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x806E
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x006D
#mwr -force 0xA000100C 0x51
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x806D
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x006C
#mwr -force 0xA000100C 0x52
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x806C
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x006B
#mwr -force 0xA000100C 0x53
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x806B
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x006A
#mwr -force 0xA000100C 0x58
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x806A
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0069
#mwr -force 0xA000100C 0x59
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8069
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0068
#mwr -force 0xA000100C 0x5A
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8068
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0067
#mwr -force 0xA000100C 0x5B
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8067
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0066
#mwr -force 0xA000100C 0x60
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8066
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014
#
#mwr -force 0xA0001008 0x0065
#mwr -force 0xA000100C 0x61
#mwr -force 0xA0001004 0x1
#after 1
#mwr -force 0xA0001008 0x8065
#mwr -force 0xA0001004 0x1
#mrd -force 0xA0001014

#2's complement output data format of channel A (register 0x8F) -default
mwr -force 0xA0001008 0x008F
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x808F
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

#2's complement output data format of channel B (register 0x92) -default
mwr -force 0xA0001008 0x0092
mwr -force 0xA000100C 0x00
mwr -force 0xA0001004 0x1
after 1
mwr -force 0xA0001008 0x8092
mwr -force 0xA0001004 0x1
mrd -force 0xA0001014

video_adc_bit_mapper.xlsx

3 days ago

0 Luke Allen 2 days ago

TI__Intellectual 1370 points

Hi Sourav,

Thank you for the detailed post! Please see the blow answers to your questions:

The zero padding will be applied to the LSBs
No, if you simply want to use the default output format as shown in Figure 7-2 in the datasheet (in your case, you will have 16-bit data, and only on DA0), then you do not need to configure the bitmapper. The bitmapper is a bit confusing from the datasheet, but you can think of it as a crossbar. It gets set automatically depending on your configuration. From there, if you want to change the order fo the bits, you can optionally configure the bitmapper.
Yes, the ADC3564 is a single channel device, so this is the only way it can operate in Real Decimation, 1-Wire mode.

I'm not quite sure about the formatting of the configuration that you attached, however here is the correct configuration for 16-bit, 1-wire, real decimation by 2 mode. The values on the left are the ADC register address, and the values on the right are the corresponding values being written to the register.

Fullscreen ADC3564_1W_16B_Real_Decby2.txt Download

Addr 	Value
0x0	0x1	// Reset
0x7     0x6c	// Set output resolution to 16-bit, 1 Wire
0x13    0x1	// Efuse reload
0x1b    0x88	// Enable bit mapper, set to 16-bit resolution
0x24    0x6	// Enable digital features, enable DDC
0x25    0x18	// Enable real decimation by 2
0x21    0xf0	// Set FCLK pattern for 16-bit, 1 Wire
0x22    0xf	// Set FCLK pattern for 16-bit, 1 Wire

Best,

Luke Allen

0 Sourav Banerjee 2 days ago in reply to Luke Allen

Prodigy 30 points

Hi Luke,

Since we’re not implementing any bit re-ordering, I believe configuring the bit mapper may not be necessary in this case. I do have a few additional queries I’d appreciate your input on:

Clock Selection for Sampling ADC Data:
When receiving ADC data via the digital interface at the FPGA, which clock should be used for sampling—DCLK or FCLK? The ADC3564 provides both clocks to the FPGA. Our plan is to create a parallel bus from the incoming data bits and observe the data using Xilinx Chipscope (Integrated Logic Analyzer).
Data Transfer Confusion Between Figures 8.32 and 7-2:
According to Figure 8.32, the Real Decimation output format shows 32 bits transferred per FCLK cycle (assuming two 16-bit samples). However, Figure 7-2, which illustrates the timing for 1-wire SLVDS, shows only 14 bits (16 in our case) transferred per FCLK cycle. This seems contradictory, as typically one complete sample [15:0] is transferred per sampling clock period—not [31:0]. Could you help clarify this?
Register 0x25 Configuration Doubt:
I noticed you've programmed register 0x25 = 0x18. Since I intend to use decimation, I’ve enabled the DDC mux, which would imply a register value of 0x98 instead. Could you please confirm whether this adjustment is correct?
Register 0x1B Configuration Clarification:
You've set register 0x1B = 0x88, but based on the register field description, bits [5:3] (BIT MAPPER RES) suggest that MAPPER_EN should only be enabled in Bypass mode. Since we’re operating in Real Decimation mode, I’ve disabled bit [7], which would result in a register value of 0x08 instead. Could you please verify this?
Clarification on 1-Wire and Channel Configuration:
As per your last response, the ADC3564 is a single-channel device. Does this mean it has only one balun/connector? I was under the impression that it has two identical but separate channels, and I was planning to use just one lane from one of those channels. Could you clarify this point?

I’ve attached a snapshot of the register configuration Excel sheet for your reference. Please take a look and let me know if any modifications are needed based on the above queries.

Thanks and regards,
Sourav

0 Luke Allen 2 days ago in reply to Sourav Banerjee

TI__Intellectual 1370 points

Hi Sourav,

Please see the below responses:

I'm not sure what you are asking when you say "which clock should be used for sampling", and I'm not sure what you mean by "create a parallel bus from the incoming data bits". However, you need both the DCLK and the FCLK because the output data is serialized. The rising edge of FCLK indicates the beginning of a sample, and the rising edge of DCLK indicates an individual data bit.
You are correct, good catch. Figure 7-2 is incorrect, Figure 8-32 is correct. The FCLK in real decimation, 1 wire mode should be Fs/2, meaning it will encompass two samples (32 data bits in your case). I will make sure we correct this in the datasheet.
The DDC Mux allows you to configure the input of each DDC. There is an option to select channel A or B for each DDC, as well as select the average of the two cahnnels. However, since this is a single channel device, there is only one option (Channel A is the input of DDC0), which is the default. Therefore, there is no reason to enable the DDC mux. It should probably be removed form the register map for this part, but I believe we used the same register map between the single and dual channel device.
Yes, that is fine.
Yes, this is a single channel ADC, meaning it has only one analog input. There is a dual channel version of this part, the ADC3664. However, if you are only using the one channel, it makes sense to stick with the ADC3564, as this device is cheaper.

A few comments regarding your config:

All registers are set to 0x0 by default, so it is not necessary to write 0x0 to these registers.
The "Must write 1" in register 0x08 is a typo, you do not need to write 1 to this field as it is 1 by default.
The LVDS output buffers in register 0x09 are automatically powered down in 1-Wire mode, so you do not need to power them down manually.
For register 0x0E, if you are using external reference this is correct.
Setting register 0x13 back to 0x0 after 1ms is not necessary. It is listed in the datashett, but we have tested and determined it is not required.
Enabling the bitmapper is not required, so register 0x1B is fine.
You do not need to enable the DDC mux in register 0x25

0 Sourav Banerjee 1 day ago in reply to Luke Allen

Prodigy 30 points

Hi Luke,

I have a few clarifications and a confirmation request regarding the configuration settings you mentioned:

Lane Power-Down Configuration:

I observed that Lane 1 of both channels is automatically powered down in 1-wire mode. Therefore, I am not modifying PDN DB1 (bit[1]) and PDN DA1 (bit[3]).

Since I intend to use only Lane 0 of Channel A, I believe I need to drive bit[2] of register 0x09 to 0x0 (as it defaults to 0x1 after reset).
Can you please confirm if programming register 0x09 to 0x00 is the correct approach?

Channel and Lane Usage Clarification:

Given that this is a single-channel ADC (with one analog input), can I configure the digital interface to use only Channel A and only Lane 0 of that channel?
I do not intend to use the remaining lanes/channels and would prefer to power them down.

Decimation and Data Width Understanding:

I understand your point on the real decimation mode(which shall be always > = 2) is that what you meant when you said "The FCLK in real decimation, 1 wire mode should be Fs/2", however for example if i would have gone for decimation 4, then FCLK would have been Fs/4, which means it should have accommodated 4x(16 bit) samples, making 64 bit per FCLK cycle (which in my case is 32 bit).

Is my understanding correct on this?I have attached a hand made diagram snapshot to you,please correct me if I am mistaken.

FLCK vs DLCK – Clock Selection for Memory Interface:

I understand the roles of FLCK (Frame Clock) and DLCK (Data Clock). To illustrate my use case:

If I need to store ADC data into AXI BRAM on the FPGA, which clock should I use for read/write operations?

Since BRAM cannot operate with two different clocks of different frequencies, and considering we typically store samples (e.g., 16-bit words) rather than individual bits, I assume FLCK should be used for this purpose.Please confirm if this understanding is correct.

Looking forward to your confirmation and guidance.

Thanks & Regards,
Sourav

0 Luke Allen 1 day ago in reply to Sourav Banerjee

TI__Intellectual 1370 points

Hi Sourav,

The reset value in the register map for bits 3 and 3 of register 0x9 are incorrect. Bits 0 and 1 default to 1, and bits 2 and 3 default to 0. This is why I have not programmed register 0x09 in my register config. The register config that I provided to you in my initial post has been tested and verified in the lab, and is correct.
Yes, this is how the ADC is being configured in the config I provided in my initial post. Since this is a single channel device, digital outputs DB0 and DB1 are powered down by default, as mentioned in my answer to question 1.
Yes, I meant to say in real decimation by 2, 1-wire mode. Your understanding is correct.
I'm not super familiar with Xilinx FPGA IP, but I dont think this is as straightofrward as you are thinking. I believe the input to the AXI BRAM block is parallel data. If this is the case, then you will have to implement some deserializer logic which uses both the DCLK and the FCLK to convert the serialized data to parallel data. Then from there, you can feed it into the AXI BRAM block, at which point you could use the FCLK if desired.

Best,

Luke Allen

0 Sourav Banerjee 20 hours ago in reply to Luke Allen

Prodigy 30 points

Hi Luke,

Thank you for the clarification. Given the numerous typos and inconsistencies in the datasheet, it's crucial that we program the device accurately.

Regarding register 0x09, as you mentioned, the default value for Bit[0] & Bit[1] is 0x1 (both powered down), and for Bit[2] & Bit[3] it's 0x0 (both powered up). Since I intend to power down lane 1 (DA1) as well, I believe I should set Bit[3] to 0x1 instead of 0x0, while leaving the other bits unchanged as suggested. Could you please confirm what the final value of register 0x09 should be in this case? Let me know if my understanding is incorrect.
As you rightly pointed out, we might need to implement some RTL logic to deserialize the incoming 16-bit data from the ADC within the FPGA. Following that, we can use FLCK for sampling or performing memory read/write operations. We’ll try take it forward and handle the implementation internally.

Thanks & Regards,
Sourav

0 Luke Allen 20 hours ago in reply to Sourav Banerjee

TI__Intellectual 1370 points

Hi Sourav,

No, you do not need to set bit 3 to 1. Lane DA1 is powered down automatically in 1-wire mode:
Yes, sounds good.

Best,

Luke Allen

0 Sourav Banerjee 20 hours ago in reply to Luke Allen

Prodigy 30 points

Hi Luke,

Thanks for the clarification. I’ll proceed with the register configurations you shared in your initial post. Given the confusion, it makes sense to follow a tested sequence and configuration. I’ll keep you updated as we move forward.

We plan to use the chip in the coming week, so I’d appreciate it if we could keep the communication channel active. Once we successfully bring up the core and start receiving data into the FPGA, we can consider the case closed.

Thanks again for your support. I’ll check in with my team over the weekend to see if there are any further clarifications needed from your end.

Best regards,
Sourav

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ADC3564: Clarification on ADC3564 RegisterConfiguration