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ADC12DJ3200EVM: SYSREF register setting to reduce the sysref frequency.

Thakur Rohit Singh
Prodigy 130 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200, LMK04828

Tool/software:

I am using ADC12DJ3200 ADC, JMODE=2, F=8, K=4 (default). When i change K=8 , I expect SYSREF frequency to reduce by half but that is not the case when seen at the FPGA side.

As per equation from the datasheet.

fsysref= R x Fclk/10 x K x Fx n

ADC register 0x202 is set to 7, 0x29 =70 , 0x2B0=01

what register setting I am missing at my end?

-trs

  • 0
    TI__Mastermind 38970 points

    Hi Thakur,

    Correct the sysref frequency expected should be different.

    However, keep in mind the sysref pins on the ADC are inputs. 

    Therefore, wherever your sysref frequency originates from, FPGA or LMK or LMX, some clocking device, this needs to change accordingly.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 130 points

    Hi  

    Thanks for your response.

    I am using ADC12DJ3200 EVM card not a custom board. In this, LMK04828 provides devclk and sysref clock to both ADC and FPGA. As i told you when i change my K value from 4 to 8 i dont see any change in my SYSREF clock period at the FPGA side. I am not sure what am i missing here. As i told ADC register 0x202 is correctly set to 7.

    Any insights to this will be appreciated.

    -trs

  • 0 in reply to Thakur Rohit Singh
    TI__Mastermind 38970 points

    Hi Thankur,

    If you need a different sysref frequency, then you need to change the LMK, not the ADC. Since the LMK device provide the sysref clocking signal.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 130 points

    Hi  

    Which LMK04828 register i need to set to reduce my SYSREF frequency? As per ADC12DJ3200 datasheet, Sysref frequency is decided as per below equation.

    fsysref= R x Fclk/10 x K x Fx n

    I am changing my K value from 4 to 8, so i assumed Fsysref will reduce by half but it is not the case when seen on the FPGA side. Please suggest.

    -trs

  • 0 in reply to Thakur Rohit Singh
    TI__Mastermind 38970 points

    Hi Thankur,

    This means the ADC itself is expecting that particular sysref frequency..... half or whatever you set the ADC to.

    If you are using the DJ3200 EVM, then you can change the clocking frequencies in the GUI, on the LMK tab.

    Then use an oscope to verify that the frequency was indeed changed.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 130 points

    Hi  

    Many thanks for your response. Can you help me verify the LMK configuration, do i need to set DCLK Divider explicitly to 20 as highlighted. For JMODE2, on programming the ADC  this DCLK divider sets to 10.

    This will reduce the Dev clk and sys ref frequencies to half of the original value?

  • 0 in reply to Thakur Rohit Singh
    TI__Mastermind 38970 points

    Hi Thankur,

    Yes, I believe that is the LMK register to change. You can probe it with an oscope to verify.

    Regards,

    Rob