ADC12DJ3200EVM: SYSREF register setting to reduce the sysref frequency.

Hi Rob Reeder 

Thanks for your response.

I am using ADC12DJ3200 EVM card not a custom board. In this, LMK04828 provides devclk and sysref clock to both ADC and FPGA. As i told you when i change my K value from 4 to 8 i dont see any change in my SYSREF clock period at the FPGA side. I am not sure what am i missing here. As i told ADC register 0x202 is correctly set to 7.

Any insights to this will be appreciated.

-trs

Hi Rob Reeder 

Which LMK04828 register i need to set to reduce my SYSREF frequency? As per ADC12DJ3200 datasheet, Sysref frequency is decided as per below equation.

fsysref= R x Fclk/10 x K x Fx n

I am changing my K value from 4 to 8, so i assumed Fsysref will reduce by half but it is not the case when seen on the FPGA side. Please suggest.

-trs

Hi Rob Reeder 

Many thanks for your response. Can you help me verify the LMK configuration, do i need to set DCLK Divider explicitly to 20 as highlighted. For JMODE2, on programming the ADC  this DCLK divider sets to 10.

This will reduce the Dev clk and sys ref frequencies to half of the original value?