• State Resolved
  • Replies 3 replies
  • Subscribers 47 subscribers
  • Views 79 views
  • Users 0 members are here
Support feedback
Options
Options
Related

ADC3563: Ramp pattern setup, DB lanes not working

Maik Ritter
Prodigy 20 points
Part Number: ADC3563

Tool/software:

Hi,

I am working with the ADC3563 and trying to verify all LVDS lanes using the built-in ramp test pattern. My setup is configured for dual-band complex decimation by 32, so I expect to see the same ramp pattern on both the DA and DB lanes. I prepared this question with the help of AI, but it really showcases my problem. The AI just finds better explanations ;-). I hope you don't mind.

Observation:

  • The DA lanes (DA0/DA1) are working correctly. I see a synchronous data pattern that matches the FCLK and DCLK. I have not yet deserialized the data inside the FPGA.

  • The DB lanes (DB0/DB1) are not working. I see a high-frequency, asynchronous signal that looks like noise.

System Configuration:

  • Device: ADC3563

  • Sample Clock (Fs): 15.3104 MHz

  • Serializer Clock (DCLKIN): 3.8276 MHz

  • Mode: 2-Wire, 16-bit, Complex Decimation by 32, Dual-Band

  • Hardware: External 100-ohm differential termination is verified to be present on all LVDS input pairs (DA and DB) at the FPGA.

    Register Initialization Sequence

    Here is the exact sequence of SPI writes I am sending to the device after a hardware reset:

    Address Value (Hex) Description
    0x00 0x01 Software Reset (bit is self-clearing).
    Wait - Wait >20ms for reset and calibration.
    0x08 0x02 Power-up ADC core and internal blocks. PDN_GLOBAL = 0.
    0x09 0x00 Power-up all LVDS output drivers (FCLK, DCLK, DA0/1, DB0/1).
    0x1A 0x00 Set LVDS drivers to full-swing mode.
    0x19 0x80 Configure FCLK source to be the DDC block for complex decimation mode.
    0x11 0x04 Power down the DLL, as required for Fs < 40 MHz on the ADC3563.
    0x24 0x0E Enable digital path and set DDC MUX to route ADC input to both DDC A and DDC B.
    0x25 0xD0 Enable the DDC MUX and set decimation factor to 32 for both channels.
    0x26 0xA2 Set 6dB gain for both Mixer A & B and assert NCO resets.
    0x26 0x88 De-assert NCO resets while keeping the 6dB gain setting.
    0x14 0x04 Configure ramp pattern step size (for 16-bit resolution).
    0x15 0x00 Configure ramp pattern step size (for 16-bit resolution).
    0x16 0x48 Enable the ramp test pattern on both Channel A (TEST_PAT_A=2) and Channel B (TEST_PAT_B=2).
    0x8F 0x00 Set data format for Channel A to 2's Complement (default).
    0x92 0x00

    Set data format for Channel B to 2's Complement (default).

My Question:

Given that the DA lanes are working plausible with this configuration, is there any register setting I have missed that is required to fully enable the DDC B data path and the DB0/DB1 LVDS drivers? The configuration seems correct according to the datasheet, but the behavior on the DB lanes indicates a problem.

Thank you for your support.

  • +1
    TI__Intellectual 1410 points

    Hello,

    Thank you for sharing the details about your issue. Yes, your configuration is incorrect. When programming the ADC3563, you MUST follow the register configuration sequence listed in Table 8-8 in the datasheet.

    Below is the correct sequence for your configuration, which I have tested and verified in the lab: 

    Fullscreen ADC3563_16B_2W_ComplexBy32_DualBand.txt Download 
    0x0     0x1	// Reset
0x7     0x4b	// Configure output interface bitmapping
0x13    0x1	// Efuse reload
0x1b    0x88	// Configure output interface resolution
0x24    0x0E	// Enable DDC, set both DDC inputs to CHA
0x25    0xD0	// Set dec factor to 32, enable DDC Mux
0x27    0x10	// set I/Q order for CHA
0x2e    0x10	// set I/Q order for CHB
0x19    0x80	// Configure FCLK settings
0x2a    ????	// Configure NCO A to desired frequency
0x2b    ????	// ...
0x2c    ????	// ...
0x2d    ????	// ...
0x31    ????	// Configure NCO B to desired frequency
0x32    ????	// ...
0x33    ????	// ...
0x34    ????	// ...
0x26    0x88	// Enable 6-dB mixer gain for NCO A and B
0x26    0xaa	// Assert phase reset for NCO A and B
0x26    0x88	// deassert phase reset for NCO A and B
0x14	0x04	// Set custom pattern to ramp pattern step size of 1 in 14-bit mode 
0x15	0x0	// ...
0x16	0x48	// Set Test pattern to ramp mode for CHA and CHB

    I included the configuration for test pattern as well. You can simply set those registers back to 0 when you want to exit test pattern mode.

    Best,

    Luke Allen

  • 0 in reply to Luke Allen
    Prodigy 20 points

    Thanks Luke!

    this did exactly what I intended. Now both channels contain the ramp pattern.

    I don't know where I lost track, since I did also try to implement the register configuration sequence from the datasheet, but it did not work, so I started to fiddle around and ended with the "configuration" I posted here...

    Anyway, your solution works flawless.

    May I ask why you switched I/Q sample order vie registers 0x27 and 0x2e? I tested also without those register writes and the ramp appears also.
    Was there some intention on your side or was it just kind of muscle memory of yours?

    Regards,
    Maik

  • 0 in reply to Maik Ritter
    TI__Intellectual 1410 points

    Hi Maik,

    Thanks for reporting back, I'm glad this fixed your issue!

    In regards to swapping the I/Q order, that is a good question. I followed the guidance for registers 0x27 and 0x2e in the table, which indicates for 2 wire mode, you should configure bit 4 (OP Order) to 1, and bit 3 (Q Delay) to 0.

    I think something may have been lost in translation when this datasheet was made, as the description for the OP ORDER and Q DELAY fields are not completely accurate. These fields must be set to the below values for their respective modes for the proper output data.

    But, as you pointed out, this does not matter for test pattern mode. It will, however impact the actual output ADC data if these are programmed incorrectly.

    Best,

    Luke Allen