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ADS131M02: Syncronous sampling to external 10KHz reference with 10kSPS sampling rate.

Jason Lee
Prodigy 95 points
Part Number: ADS131M02

Tool/software:

Hi Support Team,

I would like to achieve exactly 10 kSPS sampling rate synchronized to an external 10 kHz signal's rising edge.

Board Configuration:

  • FPGA connected to ADS131M02
  • 2 ADC input channels
  • Single-ended input: AINnP only (AINnN connected to GND)

My Strategy:

  1. Configure ADC for 64 kSPS in continuous-conversion mode
  2. Send SYNC pulse synchronized to the external 10 kHz signal's falling edge
  3. Read all ADC samples at every DRDY falling edge
  4. Accept only the ADC data sampled immediately after the 10 kHz rising edge
  5. Adjust when the SYNC pulse is generated to fine-tune where the sampling occurs within each 10 kHz period

Questions:

  • Is this approach reasonable and feasible?
  • Are there any recommended best practices or potential issues I should be aware of?
  • Would phase calibration be helpful in this application?

   BTW there seems to be a typo at table 8-2 of the datasheet( SBAS853A – JANUARY 2020 – REVISED APRIL 2021 )

   I think OSR 64 corresponds to 64kSPS

Thank you for your assistance.

Best regards,

Jason Lee

  • 0
    TI__Mastermind 45845 points

    Hi Jason,

    Your strategy 1/2/3 are good and reasonable, but the sinc3 and sinc3 + sinc1 filters for a given channel require time to settle after a channel is enabled, the channel multiplexer or gain setting is changed, or a resynchronization event occurs. The ADS131M02 does not gate unsettled data. Therefore, the host must account for the filter settling time and disregard unsettled data if any are read. The data at the next /DRDY falling edge after the filter settling time listed in Table 8-3 has expired can be considered fully settled. See 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter and  8.5.2 Synchronization section for more details in ADS131M02 datasheet. 

    Phase calibration feature is helpful when different channels are measuring the outputs of different types of sensors that have different phase responses. This does not help in your application.

    The "32ksps" in table 8-2 you highlighted is a known typo, it will be corrected in next revision for the datasheet. Thanks.

    BR,

    Dale

  • 0 in reply to Dale Li
    TI__Mastermind 45845 points

    Hi Jason,

    Your strategy 1/2/3 are good and reasonable, but the sinc3 and sinc3 + sinc1 filters for a given channel require time to settle after a channel is enabled, the channel multiplexer or gain setting is changed, or a resynchronization event occurs. The ADS131M02 does not gate unsettled data. Therefore, the host must account for the filter settling time and disregard unsettled data if any are read. The data at the next /DRDY falling edge after the filter settling time listed in Table 8-3 has expired can be considered fully settled. See 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter and  8.5.2 Synchronization section for more details in ADS131M02 datasheet. 

    Phase calibration feature is helpful when different channels are measuring the outputs of different types of sensors that have different phase responses. This does not help in your application.

    The "32ksps" in table 8-2 you highlighted is a known typo, it will be corrected in next revision for the datasheet. Thanks.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 95 points

    Hi Dale,


    Thank you for pointing out the issue.

    My calculation result of th settling time is 88.9us at 8.192MHz with OSR=64.

    It seems my system would never escape the settling state.

    I'll need to explore alternative approaches

    BR

    --

    Jason Lee