Some questions on hardware design and operation

Part Number: DDS39RFS10
Other Parts Discussed in Thread: LMX2592, , TPS7A94, TPS7A15, TPS7N53, TPS62913

Tool/software:

Planning to use DDS39RFS10 in DDS only mode w/ DES (both DES2XL and DES2XH). Clocked with LMX2592 at ~7.1 GHz Fclk. Need some clarification on these points.

5. Is <1 µVrms noise LDO (TPS7A94) essential or would anything below 10µV be good enough for VDDCLK10 and other sensitive rails? LDOs like TPS7A15 / TPS7A14 would allow for 1.2V -> 1.0V

8. Would the TCM2-722X+ balun work fine for the outputs? The eval board sch used a 3 dB T-attenuator (but 50 Ohm impedance?), is this necessary when the balun is well-matched? Or is the DAC output itself not a perfect 100ohm diff? S-parameters would help here.

9 months ago

0 Rob Reeder 9 months ago

TI__Mastermind 45670 points

Hi BH,

On #5, please stay with the recommended LDO (TPS7A94) on the EVM. This supply is sensitive. Unless your phase noise requirements for your application are lowered.

Regarding #8, TCM2 balun you mentioned above will work, I would recommend still putting in the placeholders for the 3dB T pad attenuator.

The sparams are located here for the RF10/12.

www.ti.com/.../DAC39RF12

Regards,

Rob

0 BH 9 months ago in reply to Rob Reeder

Prodigy 60 points

For #5, the phase noise (in the 1-100 KHz offset) would be fully limited by LMX2592 we intend to use. Around 20-30 dB worse phase noise at every offset, looking at the DAC additive phase noise as shown in ds. Only the "Analog PLL" has any hope of revealing the DACs noise limit.

The power savings can be far more important, unless any other LDO would limit even the 2592. Comparing 3 LDOs output noise at 10 KHz offset:

TPS7A94 - 1.5 nV/√Hz

TPS7N53 - 6.0 nV/√Hz

TPS7A15 - 20 nV/√Hz

TPS7N53 seems like a good compromise as it works with 1.2V VIN. But how does this map to the actual additive phase noise?

0 Rob Reeder 9 months ago in reply to BH

TI__Mastermind 45670 points

Hi BH,

You can check out these articles which discuss how LDO noise translates to the output spectrum.

In the case of the VDDCLK supply the PSRR is on the order of only 20dB. This is a sensitive supply to make these LDO trades, if phase noise is important specification for your application.

Regards,

Rob

https://www.ti.com/lit/an/slyt811/slyt811.pdf?ts=1759443198539&ref_url=https%253A%252F%252Fwww.ti.com%252Fsitesearch%252Fen-us%252Fdocs%252Funiversalsearch.tsp%253FlangPref%253Den-US%2526nr%253D5%2526searchTerm%253Drob+reeder+clutter

www.ti.com/.../slyt815.pdf

0 BH 9 months ago in reply to Rob Reeder

Prodigy 60 points

PSRR is a seperate concern and most of these LDOs have similar/good enough PSRR. Don't know how comparable RF-sampling ADCs and DACs are in this regard, but the second doc shows even 15-25 µVrms (40 nV/√Hz at 10 KHz) noise from TPS62913 buck has no discernable impact on phase noise?

0 Rob Reeder 9 months ago in reply to BH

TI__Mastermind 45670 points

BH, I am referring to the PSRR of the DAC. Not the LDO.

Correct, referring to the article, the ADC has a higher noise floor than the DAC.

However, the principles are the same.

Another way to test this, is to purchase the DAC EVM, test its phase noise, then swap in the other regulator and see if the phase noise is still good enough for your application. Its a lot of work, but sometimes this is what needs to be done in order to make these sort of component tradeoffs.

Regards,

Rob

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Some questions on hardware design and operation