• State
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 35 views
  • Users 0 members are here
Support feedback
Options
Options
Related

ADS9327: Max sampling rate vs number of serial outputs

Eric Wheatley
Prodigy 10 points
Part Number: ADS9327

Tool/software:

The default operation is with 4 lanes of output and one can then obtain the max sample rate of 5MS/s corresponding to 200ns per sample.  The preliminary data sheet (may 2025) says the max SPI clock (SCLK) is 65MHz and the minimum SCLK period is 16.7ns.  These are not quite consistent.  If the minimum SCLK period is 16.7ns then the max SCLK frequency would be about 60MHz.

In the default operation for data output shown in Fig 6-2, it appears that one needs 8 SCLK periods to read out the data on 4 lanes which is at least about 133ns. 

There is no similar diagram for operation with 2 lanes or 1 lane of output data but from Table 7-4 it appears that one needs 16 SCLK periods wtih 2 lane operation and 48 SCLK periods with 1 lane operation.  If this is correct, it suggests that the max sampling rate would be limited to 3.75MS/s with 2 lane operation and 1.25MS/s with 1 lane operation.  Is this correct?  If so, perhaps it could be added to the datasheet for clarity.

Is three a date when this part will be available in distribution?

  • 0
    TI__Expert 4010 points

    Hello Eric, 

    Thank you for posting on TI's E2E forum! I am happy to hear of your interest in one of our newer devices, ADS9327! 

    You are correct to notice the discrepancy on the SPI clock and the minimum SCLK period, in the preliminary stages of the release of this device we started at an SCLK frequency limit of 60MHz, hence the 16.67ns period. We also did at some point consider extending the limit to 65MHz but settled back to 60Mhz, and some values remained, showing the discrepancy mentioned. 

    We knew this device would be able to perform with faster speeds, but we wanted to ensure a reliable use case of the device during the initial stage as well as confirm with extended validation what the fastest and most reliable speed would be for this device. 

    This device is currently in the process of being fully released to market, not just as a preview, and should be available online soon. With that release, this specification will again be updated. The final released product will be rated for a faster speed and the period will be adjusted accordingly. 

    If you currently have preliminary devices, the recommended speed would still be 60MHz/16.67ns, but the device should still be functional if 65MHz is preferred. 

    As far as the sample rate to data lane ratio, you are correct, 4-lane would be ideal for the fastest sample speeds, and the 2 or 1 lane configurations would be limited to a slower sample rate. Other configurations like low latency and CS-CONVST shorted will also contribute to some sampling speed limitations depending on additional configurations. To avoid having an overwhelming amount of timing diagrams we found that timing diagrams showcasing the timing differences between default, low latency, and CS-CONVST shorted, the most valuable. The later tables explaining the SCLK needed as well as the data output format in different lane configurations would make easier to compare this lane option differences. 

    That being said, thank you for your input on the clarity on lane to max sample rate clarity though, it is greatly appreciated. We do ultimately want to make the datasheets aids to the device use and want to avoid any confusion.  I will pass this on to the internal team for any upcoming datasheet updates. 

    Also, the final version of this device in underway and should be live soon. 

    Best regards, 

    Yolanda