Tool/software:
Hi,
I am designing a board an ADS9219 (or one of his variants)
This device requires two voltage rails:
- AVDD_5V identified in the documentation as analog
- DD_1V8 that may be interpreted as digital, but old documentation had it divided in digital and analog.
The evaluation board takes no risk. It uses a dedicated LDO for each rail. This is specially energy wasteful with the 1v8 rail.
What is the analog component of the DD_1V8 rail? I would assume that is the LVDS signaling. I would also assume that noise here may affect timing.
Is there PSRR data or any recommendation on these power rails?
I intent to use a DCDC converted 1v8 power rail shared with the FPGA. I would add passive filtering.
It would also be good to use a DCDC converted 5V with passive filtering, but I am not brave enough to do it without data. I plan to use the internal reference.
Thanks!