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AFE20408: Power supply collapse - power down timing

Inho Hwang
Prodigy 20 points

Part Number: AFE20408

Tool/software:

A register configuration scheme that can satisfy the off-sequence of a GaN power amplifier using the automatic power-down function of the afe20408 GaN bias controller chip during a sudden power outage.


The timing data for Vss and Vdd collapse in Figures 5-38 and 5-40 of the datasheet appears to show simultaneous changes in PAON and DACA1 (used as Vgg pinch-off with clamp settings). I'd like to inquire about this as an appropriate off-sequence for a GaN power amplifier.

Thank you

  • 0
    TI__Genius 17430 points

    Hi Inho Hwang,

    If the AFE20408 loses VDD or VIO power, all DAC and OUT outputs will immediately clamp to the VSS voltage, and the PAON will turn off. If the device loses VSS power, the DAC and OUT outputs will clamp to VSS and follow the voltage up to ground. Turning off the VSS voltage can be dangerous if the PA is still on. Follow this for the correct shut down procedure:

    1) Set the DACs/OUTs to your pinch off voltage. 
    2) If you are using PAON, shut it off. Turn off the Drain voltage or otherwise separate it from the PA. 
    3) Once the PAON is safely shut off, you can turn off the power to the AFE20408.

    Thanks,
    Erin

  • 0 in reply to Erin Bowrie
    Prodigy 20 points

    Thank you. However, what I want is not a normal shutdown procedure.

    I'm looking for a way to prevent the GaN power amplifier from being destroyed in the event of an abrupt power-off, rather than a normal shutdown procedure.

    For example, I'm trying to design a GaN amplifier bias controller that is safe even if the power switch is accidentally turned off without performing the shutdown procedure during development and testing.


    Looking at the datasheet's Vdd, Vss, and Vio collapse diagrams, it appears that the PAON signal goes low and the OUT signal is clamped by DACA1 at the same time. How can I ensure that the OUT signal is clamped by DACA1 first, and then PAON goes low?

    Thanks

    Inho Hwang

  • 0 in reply to Inho Hwang
    TI__Genius 17430 points

    Hi Inho,

    There's no special configuration to prevent the supply shutdowns from clamping both PAON and the OUT pins at the same time, as any supply loss will automatically set the device in a reset state. Something you could try is adding a capacitor to the output of the PAON pin. Adding one could force the PAON to collapse slower than the OUT switching. This would cause the PAON to take longer to fully turn on, though.

    Thanks,
    Erin