Tool/software:
Configuration of the AFE4432.
• Internal clock: 250 kHz
• LED current: 100 mA
• Interrupt: Enabled for FIFO watermark
• Watermark level: 119 samples
• PRPCT: 1707 → Expected ODR ≈ 75 Hz
• Number of phases: 4
• Calculated PRF: CLK_PRF = 250kHz / 1707 ≈ 149.97 Hz → PRF period ≈ 6.668 ms
• Expected watermark interrupt timing: 12 PRFs × 6.668 ms ≈ 80 ms
• LED current: 100 mA
• Interrupt: Enabled for FIFO watermark
• Watermark level: 119 samples
• PRPCT: 1707 → Expected ODR ≈ 75 Hz
• Number of phases: 4
• Calculated PRF: CLK_PRF = 250kHz / 1707 ≈ 149.97 Hz → PRF period ≈ 6.668 ms
• Expected watermark interrupt timing: 12 PRFs × 6.668 ms ≈ 80 ms
Execution:
1. AFE is configured and enabled.
2. FIFO_RDY interrupt is received on a GPIO.
3. On each interrupt, 120 samples are read from the FIFO (360 bytes).
4. After data read, processing is done (in some cases).
2. FIFO_RDY interrupt is received on a GPIO.
3. On each interrupt, 120 samples are read from the FIFO (360 bytes).
4. After data read, processing is done (in some cases).
Issue 1: Inconsistent Interrupt Timing
We observe that FIFO_RDY interrupts sometimes:
• Arrive earlier than expected (e.g., < 80 ms)
• Or arrive later than expected (e.g., ~86 ms)
To capture this, we added debug logs in the firmware and also monitored the interrupt pin using a logic analyzer. No additional tasks are performed between FIFO read and wait for the next interrupt, to rule out delays from the application.
We observe that FIFO_RDY interrupts sometimes:
• Arrive earlier than expected (e.g., < 80 ms)
• Or arrive later than expected (e.g., ~86 ms)
To capture this, we added debug logs in the firmware and also monitored the interrupt pin using a logic analyzer. No additional tasks are performed between FIFO read and wait for the next interrupt, to rule out delays from the application.
Issue 2: Unexpected Sample Count on Late Interrupts
Once an interrupt is delayed, the number of samples available becomes higher than expected (e.g., 127 or 128 instead of 120), which is indefinite for all subsequent interrupts.
Example:
1. FIFO_RDY arrives at T1
2. 128 samples available
3. We read only 120 samples (to maintain phase alignment)
4. At T1 + 80 ms, the next interrupt fires, and again 128 samples are available; this happens for all the next interrupts.
We would expect:
• 8 leftover samples + 112 new = 120 → next interrupt fires
• So on the next interrupt, the available sample count should reset to 120, not stay at 128
Could you clarify:
• Why does the number stay at 128 instead of resetting?
• Shouldn’t the FIFO interrupt trigger earlier once the total reaches 120 (including leftovers)?
Once an interrupt is delayed, the number of samples available becomes higher than expected (e.g., 127 or 128 instead of 120), which is indefinite for all subsequent interrupts.
Example:
1. FIFO_RDY arrives at T1
2. 128 samples available
3. We read only 120 samples (to maintain phase alignment)
4. At T1 + 80 ms, the next interrupt fires, and again 128 samples are available; this happens for all the next interrupts.
We would expect:
• 8 leftover samples + 112 new = 120 → next interrupt fires
• So on the next interrupt, the available sample count should reset to 120, not stay at 128
Could you clarify:
• Why does the number stay at 128 instead of resetting?
• Shouldn’t the FIFO interrupt trigger earlier once the total reaches 120 (including leftovers)?
Question 1: Delayed Read After On-Time Interrupt
In some situations, we are unable to read the FIFO immediately after the interrupt due to other system priorities. The read may occur 6–7 ms after the interrupt.
Observation:
1. Interrupt fires at T1
2. Read is performed at T1 + 6–7 ms
3. At that point, 132 samples are available
4. We read only 120 samples
5. Next interrupt fires at T1 + ~73–74 ms (i.e., ~80 - 6/7 ms)
6. 120 samples available at the next interrupt
In this case:
• Are the samples still reliable, considering that the read may occur during the active portion of the next PRF cycle?
• Could this impact the integrity or alignment of the data?
• Would you recommend reading only during the deep sleep window, or is post-interrupt reading within a few ms still acceptable?
In some situations, we are unable to read the FIFO immediately after the interrupt due to other system priorities. The read may occur 6–7 ms after the interrupt.
Observation:
1. Interrupt fires at T1
2. Read is performed at T1 + 6–7 ms
3. At that point, 132 samples are available
4. We read only 120 samples
5. Next interrupt fires at T1 + ~73–74 ms (i.e., ~80 - 6/7 ms)
6. 120 samples available at the next interrupt
In this case:
• Are the samples still reliable, considering that the read may occur during the active portion of the next PRF cycle?
• Could this impact the integrity or alignment of the data?
• Would you recommend reading only during the deep sleep window, or is post-interrupt reading within a few ms still acceptable?
