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DAC8812: Design inquiry

Part Number: DAC8812

Tool/software:

Hi Team,

My board clock requirement block diagram is attached below.

The clock from the clock synthesizer need to feed as input clock to all ADC, DAC and FPGA in the board to make a synchronization.

Also from FPGA an input SYNC IN/ LDAC like input signal is fed to all the ADCs and DACs so that FPGA can control and sync activities of all the data converters.

For DAC8812 the CLK pin is used for serial clock only or can we use and CLK IN that is the mentioned in the above diagram for synchronization purpose.

 

Please provide an update on above mentioned query.

Regards,

Abhishek

  • Hi Abhishek,

    The CLK in of the DAC8812 does not enable any synchonization edges.  Only CS would enable synchronization.  You will need to ensure the CS edge is precise enough for your needs or use a device with a dedicated LDAC pin. 

    Your use case of 33MSPS is a bit difficult to address as most of our portfolio is ~<15MSPS and most of our high-speed converters are >100MSPS.