ADC3564: Request for Support on ADC3564 Configuration – 2-Wire Mode and Related Queries

Hi,

I’m currently working with the ADC3564 in our custom hardware design. Unfortunately, my initial post regarding this part seems to have been removed from the TI forums, and I’m unable to retrieve any of the previous discussions. This is quite frustrating, especially considering we’re actively using your products and rely on community support for development assistance.

I’m now revisiting the configuration with updated requirements and would appreciate guidance on the following setup:

• Interface: 2-Wire (using both DA0 and DA1)
• Resolution: 16-bit
• Sampling Rate (Fs): 125 MSPS
• Decimation (DCM): x2 (Real Decimation)
• NCO: Bypassed / Unused
• SYNC: Used only for power-down (not for synchronization, as only one ADC interface is used)

Due to certain design constraints and based on recommendations from the AMD support team, we are transitioning from a 1-wire to a 2-wire interface. This change is intended to simplify the lane rate and align with 8-bit serialization, as our current SERDES IP core supports only 8-bit output. We previously attempted 16-bit serialization via output concatenation, but this approach was deemed unreliable and not recommended.

I have a few specific queries:

1. 2-Wire Mode Configuration: Could someone provide guidance or a register configuration example for enabling 2-wire mode with the above parameters?

2. Clocking Calculations: Based on the new setup, I’ve calculated the following:

   • FCLK = Fs / (M × 2) = 125 / (2 × 2) = 31.25 MHz
   • DCLK = 31.25 MHz × 8 = 250 MHz
   • Lane Rate = (Fs × R) / (L × M) = (125 × 16) / (2 × 2) = 500 MSPS

   Could someone confirm if these calculations are correct?

3. Bit Mapping: We’re aiming to simplify the bit ordering from DA0 and DA1. I’ve attached a snapshot showing the desired bit arrangement. Is it possible to achieve this configuration? If so, I believe registers 0x39 to 0x60 need to be manually programmed. However, Figures 8-35 and 8-36 in the datasheet are a bit unclear. Any help here would be appreciated.

4. Clock Synchronization: We’re currently driving DCLKIN from the FPGA and the sampling clock from an external oscillator. The datasheet mentions that while the phase relationship between these clocks is irrelevant, they must be frequency-locked. Could someone confirm that both these clocks must be of the same frequency or not? Also, any suggestions on managing these asynchronous clocks to avoid data corruption(receive screwed up samples) would be very helpful.

Lastly, I’ve attached:

• A register configuration for the 1-wire mode(Please suggest necessary modifications for 2-wire configurations,all other parameters remain the same).
• A snapshot illustrating the desired bit reordering (related to query #3).(In the snapshot. D0 is the first bit in DA0 lane and D7 is the last bit in DA0 lane, however from pictorial observation it might look like reverse)

Looking forward to your support and guidance.

Thanks & Regards,
Sourav

ADC3564_1W_16B_Real_Decby2.txt