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ADS9219: Single DCLK, multiple ADCs (synchronized)

CRISTIAN BOGUS
Prodigy 70 points

Part Number: ADS9219

Hi Team,

        We have an application where 7 ADS9219 devices will work synchronized by the same SMPL_CLK signal (20MHz).

        The data averaging mode will be activated with the averaging set to 2 (probably). We will use the SMPL_SYNC input in order to syncronize the ADCs (one general sync pulse applied at ADC init)

        For each ADC we intend to use 2 lanes of data (DOUTA + DOUTB). 

        Our expected DCLK frequency will be:

        fDCLK=20MHz*24bits_frame/(2 (avg)*2(data_lanes)*2(DDR))= 60MHz

        We are short in FPGA available pins.

       So the questions are:

       1. Considering the fact that the ADCs are syncronized can we use a single DCLK LVDS lane for all the 7 ADCs?

        2. Applying a single synchronization pulse at init is to ensure syncronization during ADCs operation or multple/repeated SMPL_SYNC pulses are requested?

        3. Can we avoid connecting the FCLK signal at all? Since the FPGA is generating the SMPL_CLK signal and since the FPGA is clocked at 100MHz or even 200MHz we would like to emulate internally FCLK in order to spare some I/Os.

Some example code/application notes will be warmly welcomed :). The FPGA is an AMD one.

Best Regards,

  • 0
    TI__Expert 8430 points

    Hello Cristian, 

    Thank you for your questions! 

    Yes, when synchronizing multiple ADS9219s a single DCLK can be used for all devices and well as skipping FCLK altogether, so long as care is taken to calibrate and align data for all devices (for example with the test pattern capabilities of the device).  This method has been used before. 

    As far as the SYNC pin, a single pulse is needed to synchronize the devices, but additional pulses will be needed for resetting the decimation filter. 

    We do have some FPGA example code for the ADS9219 family of devices. 

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 70 points

    Hi Yolanda,

      Thank you for your insight and for the example code !

      I am aware that in a previus exchange a user managed to avoid using DCLK and FCLK alltogether by using instead calibration and alignement procedures you cite.

      But in our case we have a DCLK signal available for all the 7 synchronized ADCs. So if a DCLK is used then do the synchronization and alignement procedures are still required ? I hoped that since the frequencies are relatively small (60MHz) compared to the max frequency (480MHz) these procedures will become redundant since the potental delays will become negligible...

       If not, then what is the difference created by using DCLK signal compared to a "DCLK less" design ?

      And a last question: Could you please elaborate on why multiple SYNC pulses will be needed in order to resetting the decimation filter? Does thus mean that regularly a SYNC pluse must be issued during operation (otherwise the syncronization of ADCs may be lost)? If yes at what intervall?

    Thank you very much for your support !

    Best Regards,

    Cristian

  • +1 in reply to CRISTIAN BOGUS
    TI__Expert 8430 points

    Hello Cristian, 

    With a single DCLK for all 7 ADCs and no FCLK I would recommend some sort of synchronization/alignment as a good practice since layout considerations need to be accounted for as well. This recommendation would be with a more typical ~240MHz DCLK. 

    The FCLK is a much slower clock that is more in the realm of the SAMPL_CLK, which does make it easier to forgo, but it does help determine the start of valid data. 

    So at the typical higher speed, with multiple devices, the alignment requirement is almost necessary to ensure that the data from each device is being read correctly. 

    That being said, in your case, where the DCLK would be in 60MHz, the alignment could still help, but like you mention it could do without. In any case using the test pattern is always available. 

    CRISTIAN BOGUS said:
      But in our case we have a DCLK signal available for all the 7 synchronized ADCs

    If in this case you mean to say each ADC would have its own DCLK, then yes, additional alignment could be redundant. 

    As for the SYNC pin, only one will be needed for synchronization at the start. Any further for synchronization purposes would only be when there is a system reset/reconfiguration or as a best practice with an occasional sync if the device is running for long periods of time (the latter one is not required, but just recommended). 

    Similarly for the decimation filter, additional SYNC pulses would only be required if there was a system reconfiguration and/or some reset required. If the decimation factor remains the same additional SYNC pulses are not needed. 

    My apologies for the confusion on my end. 

    Best regards, 

    Yolanda 

  • 0 in reply to Yolanda Gonzalez
    Prodigy 70 points

    Thank You very Much Yolanda!

    Best Regards,

    Cristian