ADS131E04: Unable to Read ID Register (0x00) on ADS131E04 via SPI

Hi Dale LI,

Thanks for your response,

Initially, I was unable to read the correct register values, but after adding a 2 µs delay between two SPI bytes, I’m now able to successfully read the ID register (0xD0) and verify all written register values correctly using RREG commands.
whenever i try to write or read data,MISO is responding to the 1st BYTE of the clk itself but  i receive the proper data in the expected clk byte also
However, I’m facing an issue where CH0 always reads full-scale (0x7FFFFF), even when applying a valid DC input. Other channels return 0x000000.

Test Setup

Device: ADS131E04

AVDD / AVSS: 5 V / 0 V

DVDD: 3.3 V

SPI Clock: 10 MHz (MODE0)

VREFP–VREFN: Internal 4 V reference

Gain: 1 (Full-scale range = ±4 V)

Input:

AIN0P → +1 V DC 

AIN0N → GND (internal reference buffer connected 2.5V )

Register Setup Sequence:
ads_send_command(RESET); // 0x06
DELAY_US(200);
ads_send_command(SDATAC); // 0x11, Stop continuous read

ads_write_reg(CONFIG3, 0xEC); // Internal reference buffer, op-amp enabled
ads_write_reg(CONFIG1, 0xF2); // 16kSPS, CLK settings
ads_write_reg(CONFIG2, 0xE0); // Internal reference enable, test signal disabled
ads_write_reg(CONFIG4, 0x00); // Default
ads_write_reg(CH0_CFG, 0x10); // CH0 = normal input
ads_write_reg(CH1_CFG, 0x80); // CH1 powered down
ads_write_reg(CH2_CFG, 0x80); // CH2 powered down
ads_write_reg(CH3_CFG, 0x80); // CH3 powered down

// Read the ID register (returns 0xD0 correctly)

ads_send_command(START); // 0x08
DELAY_US(1000);

ads131e04_read_all_channels(channels_raw);

Observation

CH0 output is always 0x7FFFFF (full scale).

CH1–CH3 output are 0x000000.

Question

Could you please suggest possible causes for the ADC reading full-scale values even with a valid analog input (1 V DC)?

attached the clk,mosi,miso,cs waveforms,






Is this early MISO activity (on the first byte) expected behavior from the ADS131E04?







As shown in the waveform, the first status byte (0xC0) appears both during the first and second clock byte cycles. Ideally, it should appear only during the second clock byte, but it seems to be duplicated or shifted early on MISO.

refer the below image,



Please let me know if need any other details to debug the issues. 

Thanks, 
Saravana kumar M

Hi TI Team,

We’re currently facing a bottleneck in our project due to this issue, and it’s blocking our progress. We’ve tried multiple approaches but are still unable to resolve it. Kindly help us to identify the root cause and provide guidance to resolve this at the earliest.

Few Additional Details about the issue:

We are following the voltage-sensing topology shown below — the negative input is biased at 2.5 V using the internally generated OPAMP_REF.

We are feeding a 1V DC input to Channel 1, but the ADC output always shows a maximum hexadecimal value or some random value when reading the data.

Please refer to the attached image for our connection topology (Figure 58: Simplified Current-Sensing Connections).

Your timely support will be greatly appreciated.

Thanks & Regards,
Manikandan V

Hi Manikandan,

I am really sorry that we are unresponsive this week. The application experts for this device are all out of the office this week.

Your SPI communication looks correct to me. You can simply disregard the first byte on MISO while you are transmitting the RDATA command on MOSI. The first byte will always be (0xC0 + FAULT_STATP[7:4]). The important data starts with byte two on MISO, again with (0xC0 + FAULT_STATP[7:4]).

The channels which are powered down always read 0x000000. That is correct.

Why channel 0 reads 0x7FFFFF is not clear to me yet either. As a first debugging step I suggest to set MUX0[2:0] = 001b. This will short the positive and negative analog inputs to mid-supply internally. You should then read a value close to 0V. Please try that and report back.

Regards,
Joachim Wuerker

Hi Joachim,

Thank you for your response and guidance.

As suggested, I configured the device for the internal short test by setting MUX0[2:0] = 001b. After enabling this configuration, the output values are now reading close to zero across all channels, as expected.

I’ve attached the measurement results and the configuration snapshot for your reference.

Please check and let me know if there are any additional checks or configurations you would recommend next.

Thanks and regards,
Manikandan V

Hi Manikandan,

thanks a lot for performing this test. It looks like the ADCs are converting properly and you can read the conversion data.
Which register bits do your "status = 0x00D0" refer to?

As a next step you can apply a known signal on the inputs again. I suggest to start with something simple. The device does not support single-ended measurements where the negative analog input is connected to AVSS, but for debugging purposes we can use that. Means connect INxN = AVSS and for example INxP = 1V. Don't drive the INxN input with the buffer or anything to level-shift it for now. You should read a value slightly less than 1V in this case.

If this works, then we just need to find out what is wrong with your circuit implementation according to Fig. 58.

Regards,
Joachim Wuerker

Hi Manikandan,

that is very weird. Can you confirm you are not connecting anything else to the channel 0 inputs besides the 1V signal on AIN0P and GND to AIN0N?
Have you confirmed the voltages on both pins with a DMM?
Previously you mentioned "AIN0N → GND (internal reference buffer connected 2.5V)"

Have you tried any of the other channels?

Regards,
Joachim Wuerker

Hi Joachim Wuerker,

Yes, the connections are correct. We are applying approximately 0.999 V on AIN0P, with AIN0N connected to GND.

When measured using a DMM between AIN0P–GND and AIN0N–GND, the voltage fluctuates between 1.5 V and 1.8 V, eventually stabilizing around 1.8 V. Currently, there is no internal reference buffer connected to AIN0N, and the internal OPAMP_ buffer is disabled.
We also observed the same behaviour on other channels during testing.

In my configuration, VREF = 4 V and gain = 1. However, the ADC output appears to saturate when the input voltage exceeds approximately 250 mV, which does not align with the expected ±4 V full-scale range at gain = 1.

Additionally, the ADC counts fluctuate by about ±30,000 across all tested voltage levels.

Below are the measured results for different DC input levels:

VREF = 4 V, GAIN = 1

VREF = 2.4 V, GAIN = 1

Please let us know whether this can occur due to any connection issues or capacitor placements in the Analog power and VCap pins ? 



Thanks and regards,
Manikandan V

Hi Manikandan,

I think this would be a good time to review your schematic for any issues as it is quite puzzling what is happening here. Could you please share the schematic with me for review?

From the output codes it looks like as if a gain = 16 is used.
I do currently not have a good explanation for why you would measure 1.5V to 1.8V with the DMM on AIN0P.

Have you tried any measurements without configuring the ADS131E04 at all? Just use it in its default register configuration?
You might at least have to set PDB_REFBUF = 1b though when using the internal VREF.

Regards,
Joachim Wuerker

Hi Joachim Wuerker,

Yes, you are correct — the issue was due to a dry solder joint on the VREFN pin connection to ground. After re-soldering, the ADC output counts now respond correctly according to the input voltage.

Below are the test observations for input voltages from 0 V to 4 V. The measured ADC counts closely follow the expected values, confirming that the reference and input circuitry are functioning properly.

From the data, we observed a variation of approximately 5000–7000 counts, corresponding to about 3 mV offset.

Could you please confirm if this level of deviation is normal for the ADS131E04 device, or if there are ways to further optimize/reduce this error?

Thank you for your continued guidance and support.

Additionally, we need a few clarifications regarding timing optimization and sampling behavior of the ADC. We’ll share our observed timing data and follow up with further details soon.

Best regards,
Manikandan V

Hi Manikandan,

thanks a lot for the positive news. I am glad you found the issue on the PCB.

How did you apply the 0V to 4V signal?
As mentioned previously, the device does not allow single-ended measurements where INxN is connected to GND. I just had you use this configuration for debugging purposes. If you used a single-ended measurement, then I am not surprised to see this offset/non-linearity.

When using Gain=1 you will have to level shift the signal at least by 300mV. Means you can set INxN = 300mV for example and then sweep INxP from 300mV to 4.3V to create a differential input signal ranging from 0V to 4V.

Beyond that, you can implement a self-offset calibration by leveraging the internal short connection you tested previously.
And then you could also implement a system gain calibration to get rid of the initial gain error and VREF inaccuracy.

Regards,
Joachim Wuerker 

Hi Joachim Wuerker,

We are currently providing the input signal from a Digilent Analog Discovery 2 device using crocodile clips.
At the moment, the IN1N pin is connected to the Digilent negative output (GND), and the IN1P pin is connected to the positive terminal of the Digilent device.

I’m still not completely clear about the DC bias requirement on the IN1N pin — could you please explain this in a bit more detail?

As suggested, we will proceed with implementing the device self-offset and gain calibration routines.

Below are the details of our input signal conditions:

1. –125 mV to +250 mV DC signal — with step increments of 2 mV.

2. 0 V to 4 V, 400 Hz sine wave — with step increments of 50 mV.

   • The sine wave is single-ended and positively biased.

   • Our original source signal is a ±2 V sine wave, which we bias through a differential op-amp stage (with reference voltage) to create a 0–4 V swing before feeding it into the ADC.

   • This setup was originally designed for a single-ended ADC, and the PCB is already fabricated. We later switched to this simultaneous sampling device to optimize acquisition timing.

We have approximately 25 analog input channels with different voltage scaling configurations. Each channel is conditioned to fall within the ADC’s readable range.
Our lowest input signal amplitude is 2 mV, and we’d like the ADC to be able to accurately capture such small levels.

Could you please suggest the recommended configuration or best approach for using the ADS131E04 to handle these signal conditions effectively?

Thank you once again for your valuable support and guidance.

Below is the example image of our ADC input : 

Best regards,
Manikandan V

Hi Manikandan,

the common-mode input voltage range limitation is due to the PGA that is used in front of each ADC channel. As with any traditional instrumentation amplifier, the PGA requires a certain common-mode input voltage to operate. Equation 4 in the datasheet represents this limitation. It is always a bit hard to interpret this equation unfortunately. For gain = 1, all the formula is saying is that both INxP and INxN need at least 300mV headroom from either supply rail at all times. If that headroom is not met, then the PGA outputs would saturate leading to non-linear behavior.

One solution for your 0-4V sine wave signal measurement would be to level shift the whole signal (both on IN1N and IN1P) by 300mV to 500mV. Alternatively, you could connect IN1N to 2V, and then attenuate the sine wave signal on INxP so it swings 2V +/-1.7V. Having IN1N = 2.5V and IN1P swing 2.5V +/-2V would work as well. Lastly, you could also operate the ADS131E04 with a bipolar analog supply (+/-2.5V). That way you could directly measure the +/-2V sine wave signal.

Regarding your DC signal. Please note that you cannot measure signals below GND when using a unipolar analog supply.

Regards,
Joachim Wuerker