ADS61B49: ENABLE LOW SPEED MODE

ttd

Part Number: ADS61B49

The previously designed board incorporates the ADS61B49IRGZT. A failure was confirmed in this component, and we replaced it.

After replacement, phase alignment errors began occurring. Debugging revealed that switching the ENABLE LOW SPEED MODE setting on/off resolved the issue.

Therefore, I have questions

The Revision History shows a change from A to B, but I don't believe there were any changes or errata specifically related to Q2 and Q3.

The setting switch instruction mentions 100MSPS,but what is the actual threshold value?If possible, it would be helpful to know the component variation as well.

From 2018 to 2025, were there any changes to the threshold?

If there were any other minor changes to functions between 2018 and 2025, please let me know.

Best Regards,

ttd

11 months ago

0 Kang Hsia 11 months ago

TI__Guru* 83675 points

Hello

I can only find the following history. I did not find anything else in the database.

Please advise the exact failure so I can look further into this.

-Kang

0 ttd 11 months ago in reply to Kang Hsia

Mastermind 9435 points

Hi Kang,

Thank you for your reply.

Sampling rate is 100MSPS. If Low speed mode is Enabled, then setup hold margin between output clk and data is increased.

So FPGA can recieve clk and data easly. Is it correct?

Best Regards,

ttd

0 Kang Hsia 9 months ago in reply to ttd

TI__Guru* 83675 points

continuing on this thread

RE: ADS61B49: About LowSpeed mode

TTD,

Low speed mode simply adjust the internal clocking circuitry to optimize ADC performance at lower speed range. Unfortunately, I do not have additional insight into the exact nature of the design.

-Kang

Data converters

Data converters forum

ADS61B49: ENABLE LOW SPEED MODE