ADC128S102: ADC128S102 Inter modulation distortion

Hi Muhammed,

I believe in the previous thread, you mentioned you had an issue with noise on the source. Were you able to resolve this issue? Can you share what source you are using for your testing? For characterization, we use a high precision, low-noise source, though this characterization was done some time ago by National Semiconductor, so I'm not too sure what instrumentation was used here.

Usually, we apply a window to reduce spectral leakage that occurs due to non-coherent sampling. Are you sampling coherently, and if so, how are you synchronizing the ADC clock with the signal source? Commonly we use a 7-term Blackman-Harris window.

Also, are the trials with different devices, or are they the same test with the same device?

Regards,
Joel

Hi Joel,

Thanks for the response.

The data shown are for the same device for 30 loop run.

The instrument used here is 16 bit function generator which is a good instrument for a 12 bit ADC and the signal from the instrument is pure enough.

ADC clock instrument and signal source are synchronised with same 10Mhz reference clock.

Fa = 20.5kHz, Fb = 19.5kHz

Fs=1000000

N=36000

No windowing is used since the signals tones are not leaky and coherent

Reconstructed waveform from DUT output:


Spectrum from DUT output:


Please suggest if there is any known coherency and test condition that would give repeatable results.



Regards,

Muhammed Esa A

Hi Muhammed,

I think I will need some time to discuss this issue with my team. Allow me some time to review this and get back to you. 

To help our analysis, are you able to share time domain data of your trials with us? You can attach it here as a .zip if the data is available.

Regards,
Joel

IMD_LOOP_DATA.zip
Hi Joel,

Please find the attached file for the IMD test digital data of ADC128S102 for 5 loop.


Regards,

Muhammed Esa A

Thanks. I'll take a closer look with our own data analysis tools and get back to you.

Hi Muhammed,

There are four 2nd order IMD products to consider, all must have integer multiple cycles within the sampling window(36,000 samples). 

How are you ensuring integer multiple cycles during the sampling window for the following 2nd order IMD products? 

1. f2-f1

2. 2f1

3. f2+f1

4. 2f2

Also, are you using the 10MHz clock as the ADC clock directly?

Regards,
Joel

Hi Joel,

Please find the below image for the bin calculation.

An individual clock source is being connected as ADC clock source,and the same is synchronised.

would you mind sharing the test condition and the post processing being followed by TI for the same,because that would be helpful for the further experiment.


Regards,

Muhammed Esa A

Hi Muhammed,

This device was originally characterized by National Semiconductor. I don't believe we would have the methods used originally. What I am trying now is to generate an FFT of your data both with a rectangular window, and a Blackman-Harris window, and check to see if that is what might be showing bad results.

In the case that it is, it could be due to the above, in that the higher order IMD components also need to have an integer multiple of cycles in the sampling window. 

Admittedly, we are less familiar with IMD than other AC specs. Can I ask what your case is to be concerned about IMD specifically?

Regards,
Joel