ADS9110: Powersequencing

Hello Thomas!

Welcome to TI's E2E Forum! Thank you for your question! 

We do not have a particular power up sequencing required for the ADS9110.  Is there a particular scenario in mind that you wanted to confirm was compatible with the ADS9110? 

Best regards, 

Yolanda 

Hey Yolanda,

Unfortunately I don't have a specific power up sequence. During hardware bring up tests I observed ADS9110 not responding to reset signal correctly, after powering up ADS9110. Because of lab equippment digital IO's were feeded first, after an undefiened time analog and digital supply were powered. this "hunging" is very sporadically and seldom to reproduce.
Nevertheless I want to double check, if this behaviour is possible!

Best regards,
Thomas  

Hello Thomas, 

Would you be able to share the schematic of the ADS9110 in you hardware set up? 

Is there individual control of the reset pin? or is it tied to a supply via a pull up? 

Would it be possible to do perform a HW reset after all the supplies are powered up?

Best regards, 

Yolanda

Hello Yolanda,
yes we have a individual control of ADC's reset pin. All ADC's controll pins are directly connected to a FPGA. After powering up the ADC is reseted by its RST input pin with a high -low - high pulse. Analog, reference and digital voltage rail are poering up in parallel while they are feeded by one power source. Control pins of ADC can be driven before ADC's power rails are active! There is also a pulldown at RST bin to keep ADC in Reset while FPGA IOs are not configured.

Hello Thomas, 

Thank you for sharing that. Would you still be able to share a schematic of the ADC? 

Is there any way that there is any toggling on the digital lines before the supplies are fully ramped up? 

How long is the RST pin H-L-H pulse?

Best regards, 

Yolanda