ADS131A02: Gain Switching During Communication

Hello Marvin,

Any time there is a step input change to the ADC modulator, the internal filter will require some amount of time to settle.  Maximum settling time will be 3 conversion periods since the internal digital filter is a SINC3 filter, and will require a total of 4 DRDY pulses, as shown in Figure 51 of the datasheet.

I am not certain where 20 conversion cycles comes from.  Please ask for clarification on what the customer means by 20 conversion cycles.

Also, when the digital filter is settling, although readings 1 and 2 in Figure 51 are unsettled and not accurate representations of the input voltage, these readings can be used for diagnostic purposes to detect step input changes.

Regards,
Keith Nicholas
Precision ADC Applications

Thanks for your reply.

Below is the response from SPI.

For a single channel, starting from [1], I recorded the changes when the input was 0.1V and the gain was changed from 1x to 8x, one scan at a time.
The scan period is every 63ns, with OSR set to 32. The values change with a delay, and it is unclear whether this depends on the scan time, the number of scans, or some other factor. 

Since it has not reached a steady state after three cycles, we recognize that other factors are involved.

I would greatly appreciate any insights or advice you could provide on this matter.
Thank you very much for your time and support.

Best regards,

Takeru Nakanishi

Hello Takeru Nakanishi,

Please confirm the state of M0,M1,M2 pins; what SPI configuration are you using?

Also, in order to help debug, please capture using a logic analyzer or scope the SPI bus over multiple SPI frames.

SCLK, DOUT, DIN, /CS, and /DRDY. (/DONE optional).

This will help determine if there is something configured incorrectly with the ADS131A02.

Also, I do not understand 'scan period is every 63ns'.  Using OSR set to 32, and fmod=4.096MHz, you can expect a data rate of 128ksps, or a conversion period of 1/128k=7.8us (micro-seconds).

What is your CLKIN frequency?  What are the settings for CLK_DIV and ICLK_DIV?

Regards,
Keith Nicholas
Precision ADC Applications

Hello Keith Nicholas.

Thanks for your reply. Sorry for the delay on my end.

Currently, it is operating in a daisy chain configuration. Therefore, the M0 pin is floating except for the first ADC.

The detailed operating conditions are shown below.

9 units are connected in a daisy chain configuration.

M0:The first character is Vdd, followed by a float.

M1:GND(24bit)

M2:GND(Hamming code word validation off)

fmod = 16.384MHz(External input)

OSR:1101(fMOD/64)

ICLK_DIV:100(fMOD/8)

ICLK_DIV:001(fMOD/2)

Best regards,

Takeru Nakanishi

Hello Takeru Nakanishi,

Thanks for sharing those information. Do you have the exactly same connections for the digital pins including /DONE as shown in the following figure?

The timing you shared does not help because I can not zoom in and check the details. Can you share the timing file if you can save the timing data in a logic analyzer? It would be good to include /CS and /DRDY signals.

I noticed that the CLK signal in your timing does not have the same ~50% duty cycles, some of them are narrow and some of them are wide, can you please clarify it? is this the SCLK?

According to your configurations, your data rate is 32ksps which is 32.25us, can you please clarify "scan period is every 63ns"?

BR,

Dale

Hello Dale Li

After conducting the remeasurement, we confirmed that the gain change was reflected within 3 cycles following the adjustment.
We sincerely appreciate your thoughtful consideration from multiple perspectives in addressing this matter.
We look forward to your continued support.

BR,
Takeru Nakanishi