Part Number: TSW14J58EVM
Other Parts Discussed in Thread: AFE7950EVM, , AFE7950
Hi Experts,
I'm using a TSW14J58EVM together with the AFE7950EVM.
Starting the evaluation with Latte SW V2.8, initialisation and configuration of EVMs worked as expected, no problems testing different configurations.
After some hassle when installing the newly released Latte V2.9 I got the new version finally started.
But now my test configuration (ADC/DAC default settings, RX/TX center frequency=9500MHz, BW set to 1000MHz, JESD204C encoding (autoselect)) fails with error messages when initialising the EVMs.
The log file reports the following problem with a bit file:
"Mismatch in the FPGA bit file version. AFE JESD Protocol is 204C but the FPGA bit file is 0x204b"
Using lower bandwidth configurations (requiring only JESD204B) works normally.
Is there a known issue with Latte V2.9 SW ?
Is it possible that the upgrade to V2.9 caused this issue ?
Or does this indicate that there is a defect on the EVM (probably the TSW14J58) ?
AFE7950 configuration screen: 
Complete Log File:
AFE79xxLibraryPG1p0 True spi - USB Instrument created. resetDevice Kintex RegProgrammer - USB Instrument created. Kintex RegProgrammer - USB Instrument created. Power Card - USB Instrument created. Version : 0x104204b Connected to Capture Card Loaded Libraries #================ ERRORS:0, WARNINGS:0 ================# #================ ERRORS:0, WARNINGS:0 ================# Version : 0x104204b Connected to Capture Card ################################################################### For bandwidth greater than 600MHz, Feedback Channels cannot be supported Switching to 204B JESD Mode Lane rate exceeded the Maximum Lane Rate(Mbps) value entered. Switching to 204C JESD Mode The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 24330.24 laneRateFb: 24330.24 laneRateTx: 24330.24 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 24330.24 laneRateFb: 24330.24 laneRateTx: 24330.24 Matched for 204C mode:477 Connect 10MHz reference clock at LMK_CLK_IN (J14) connector, for EVM synchronization Generated system parameters successfully Refreshed GUI ################################################################### The External Sysref Frequency should be an integer factor of: 3.84MHz 2T2R1F Number: 0 Valid Configuration: True laneRateRx: 24330.24 laneRateFb: 24330.24 laneRateTx: 24330.24 2T2R1F Number: 1 Valid Configuration: True laneRateRx: 24330.24 laneRateFb: 24330.24 laneRateTx: 24330.24 LMK Clock Divider - Device registers reset. LMK Clock Divider - Device registers reset. REFCLOCK is used from LMK source, ensure board connections are ok to do the same FPGA Reset device not found Resetting FPGA. Version : 0x104204b Connected to Capture Card Mismatch in the FPGA bit file version. AFE JESD Protocol is 204C but the FPGA bit file is 0x204b LMK and FPGA Configured. DONOT_OPEN_Atharv_FULL - Device registers reset. chipType: 0xa chipId: 0x78 chipVersion: 0x11 AFE Reset Done Fuse farm load autoload done successful No autload error Fuse farm load autoload done successful No autload error AFE MCU Wake up done and patch loaded. PLL Locked AFE PLL Configured. AFE SerDes Configured. AFE Digital Chains configured. AFE TX Analog configured. AFE RX Analog configured. AFE FB Analog configured. AFE JESD configured. AFE AGC configured. AFE GPIO configured. Sysref Read as expected Setting RBD to: 15 Setting RBD to: 15 ###########Device DAC JESD-RX 0 Link Status########### Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Serdes-FIFO error for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 BUF State TX0: 0b01010101 . It is expected to be 0b11111111 Couldn't get the link up for device RX: 0; Alarms: 0xfe00 ################################### ###########Device DAC JESD-RX 1 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Serdes-FIFO error for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 BUF State TX0: 0b01010101 . It is expected to be 0b11111111 Couldn't get the link up for device RX: 1; Alarms: 0xfd00 ################################### AFE Configuration Complete Function Execution Failed: setGoodRbd Function Execution Failed: setGoodRbd Function Execution Failed: setGoodRbd ###########Device DAC JESD-RX 0 Link Status########### Serdes-FIFO error for lane 0: 1 LOS Indicator for (Serdes Loss of signal) lane 1: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Serdes-FIFO error for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 BUF State TX0: 0b01010101 . It is expected to be 0b11111111 Couldn't get the link up for device RX: 0; Alarms: 0xfe00 ################################### ###########Device DAC JESD-RX 1 Link Status########### LOS Indicator for (Serdes Loss of signal) lane 0: 1 Serdes-FIFO error for lane 0: 1 Serdes-FIFO error for lane 1: 1 LOS Indicator for (Serdes Loss of signal) lane 2: 1 Serdes-FIFO error for lane 2: 1 LOS Indicator for (Serdes Loss of signal) lane 3: 1 Serdes-FIFO error for lane 3: 1 Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane2: False; Please check if the transmitter is sending data and eye is good. Comma Align Lock Lane3: False; Please check if the transmitter is sending data and eye is good. CS State TX0: 0b00000000 . It is expected to be 0b10101010 BUF State TX0: 0b01010101 . It is expected to be 0b11111111 Couldn't get the link up for device RX: 1; Alarms: 0xfd00 ###################################
Regards,
Harald
