DAC61416: Frame Error Checking Time / from CS signal to ALMOUT signal

Hi Hiromu-san,

I will check with my team and get back to you by tomorrow.

Thanks,
Sanjay 

Hi Sanjay,

OK, let me know once you get the info.

Regards,
Hiromu

Hi Hiromu-san,

There is no direct way to estimate this time from CS rising edge to ALMOUT output from datasheet and design team needs time to do simulation to get a faithful number. For now please ask customer to add 0.25 ms delay before measurement of the ALARM OUT. 

I would be able to provide this data by next week. Hope that's okay.

Thanks,
Sanjay 

Hi Sanjay,

As the feedback, 0.25ms is too slow.

Before confirming acculate timing of that, could you tell me which way is faster?:

It is written in the datasheet that the error can be confirmed by the CRC-error bit on the next read access where the CRC error occurred.(6.5.3) Since the SCLK is a maximum of 35 MHz, I feel that it can be reflected in ALMOUT in a few usec. If it is too late to reflect information to ALMOUT, I think it will be confirmed by SDO, but what do you think?

Regards,
Hiromu

Hi Hiromu-san,

Once configured, CRC - error signal ()if there is any) comes to the ALMOUT pin first of the device DAC81416 and not on SDO line. 

Thanks,
Sanjay