ADS7883: Title: ADS7883 – Clock and Sample Rate Limitations at 3.3 V

Hello TI Team,

I’m working with the ADS7883 SAR ADC and have a couple of questions regarding its performance at different supply voltages:

1. Clock Frequency:
   The datasheet mentions that the device supports up to 48 MHz SCLK when VDD = 4.5 V to 5.5 V, and 32 MHz SCLK when VDD = 2.7 V to 4.5 V.

   • At 3.3 V, is it strictly limited to 32 MHz, or is there any margin for higher clock rates?

2. Sample Rate:
   The datasheet specifies 2 MSPS for VDD = 2.7 V to 4.5 V and 3 MSPS for VDD = 4.5 V to 5.5 V.

   • Why is the maximum sample rate dependent on supply voltage?
   • Is this due to internal SAR timing constraints, or other factors?

I want to confirm if achieving 3 MSPS at 3.3 V is possible in any scenario, or if it’s fundamentally limited by the device.