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ADS8689: +/-256 points errors in converted values at certain input levels

Roberto Benevelli
Prodigy 20 points

Part Number: ADS8689

In a new analog input board we use ADS8689IPW A/D converter.

During debugging we noticed a strange behaviour of converted values: (only) at certain levels of input voltage the converted points have an everage value (the expected one, corrisponding to the converted voltage input), but also there are a lot of values at other two different and precise levels, both distant exactly ±256 points from the expected value. Apparently these values are wrong ones.

And this pattern occurs every 20mV (again corresponding to 256 points, because we use unipolar 5.12V input range). On every other input voltage level different from these 20mV multiples the conversion results are perfect and only have one well defined average value.

In our application the ADC has 5V single power supply and it uses internal voltage reference. The SPI signals are precisely managed by an FPGA, with conversion time 5us and acquisition time 75us, with communication at 2MHz and 16 bits frames. (Initial configuration is a "one-shot" 32 bits 0xD014_000B frame after power-on.)
We do not use RVS pin, but during debugging we verified that conversion time is always 1us, even during wrong result values. Besides, at wrong conversions we also verified that the wrong binary results effectively corrispond to SDO signal bits (that is SPI communication is ok).

During debugging with gradually excluded all others circuits external to the ADC. We by-passed analog input conditioning stages, finally connecting input source directly to the ADC (without noting differences in the problem). We verified the problem with different input voltage generators (Fluke 724 calibrator, FNIRSI SG-004A signal generator, simple linear power supply and even simple battery). We monitored power supply voltage without finding differences between good and bad conversions, and even replaced the original power supply from the board with an external DC lab one. We monitored voltage reference (and even disconnected all external high-impedance circuit) without finding differences between good and bad conversions. 

The ADC schematic is as from indications of its datasheet. On input pins, AIN_P and AIN_GND, there are 1kR series resistors and 1nF parallel capacitor.

Attached you find an image of approx 1300 conversion values at different input levels, and you can easily see the error values at two well-defined levels - 28160pts~2.2V and 28416pts~2.22V.
Attached you also find the schematic of ADC and an oscilloscope image of SPI frame.

What is the problem? Is it a known problem? How can it be solved (other than sw-averaging)?

Thanks, Roberto.

conversions.jpgschematic.jpgspi.jpg

  • 0
    TI__Expert 7670 points

    Hello Roberto,

    Thank you for posting on TI's E2E forum! 

    To make sure I understand, there is a repeatable issue where the data that is read back has a ±20mV consistently, correct? This also happens every time the input increases by 20mV correct? 

    If the sclk clock was increased or decreased does the ±20mV noise occurrence happen sooner or later instead of the consistent 20mV DC jump? 

    Or if the DC is kept steady, like at the 2.2V input or 2.22V input,  would the ±20mV noise happen again? or is it just once? 

    Also, when measuring the 1300 conversion results, was it a continuous data read or was the data collected in batches to conform to a controllers memory? 

    Best regards,

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 20 points

    Hi Yolanda
    Correct: there is a repeatable issue in which the read back data have many samples "distant" ±20mV.
    Correct: this happens every ±20mV input variation.
    I wasn't able to change SCLK frequency (which anyway should not be suspected nor connected to ADC conversion) and I haven't done tests in this sense.
    The problem is not just once but frequently at the right (i.e. wrong) level, as you can easily see also from the conversion image.
    The 1300 samples were taken in a continuous conversion test, just increasing the input value on and on.

  • 0 in reply to Roberto Benevelli
    TI__Expert 7670 points

    Hi Roberto, 

    We can skip the SCLK frequency variation, what I wanted to see if the same  ±20mV input variation would repeat corresponding to a specific frequency. 

    With the same SCLK speed, would you be able to keep the input constant in a known 20mV variant input and see if the spread is ±20mV spread is constant, or if it eventually stops.

    Also, these 20mV steps, the once with the spread (2.2V & 2.22V ) are they also repeatable, meaning if you POR the device and input those voltages directly is the spread always present? 

    Lastly, if you try the larger unipolar range, 2.5*VREF, does this issue occur again but in larger steps? 

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 20 points

    With double range (2.5VREF=10.24V) the issue occurs in the same way: again with same error ±256pts, and every same 256pts input voltage step, that is 40mV now, and very same input voltage error levels.
    Attached you find now the image of the 1300 conversion values with the new range, at the same input levels than before: now you can see the error voltage levels 14080pts~2.2V and 14336pts~2.24V.

    Besides, once the problem is present, it remains repeatable also if we turn AVDD off/on and even if we turn both AVDD/DVDD off/on (of course in this case re-configuring the ADC input range at the start).

    We also tried to half SCLK frequency and the problem doesn't change (same errors and same steps at fixed input range).

    By the way the same effect was confirmed also on other sample boards with different ADS8689 samples (and different lots).

    Couldn't the 256pts repeatability suggest some effect related to A/D conversion process?
    (It corresponds to an error which affetcs only the 8th bit and not the other lower bits of A/D conversion.) 

  • 0 in reply to Roberto Benevelli
    Prodigy 20 points

    Waiting for kind reply...
    Best regards, RB.

  • 0 in reply to Roberto Benevelli
    TI__Expert 7670 points

    Hello Roberto, 

    Apologies for the delay, I was out of office for some time. 

    Yes, this does seem to be a concern with the 8th bit. 

    Thank you for confirming this issue also occurs on multiple devices, could you please share on how many and any sample device number/lots? 

    Are there any devices that do not have this issue? or do all devices you have show this issue? 

    Best regards, 

    Yolanda 

  • 0 in reply to Yolanda Gonzalez
    Prodigy 20 points

    So far we used four/five devices (all marked 43KG4 AJZL) because this is a new design, but in all the boards they had the same behaviour, and we finally isolated the problem in ADS8689IPW, as previously explained.

    We need to know if this issue is known and how it can be solved and if we can proceed with this A/D converter or otherwise we need to switch to another model or even another manufacture.

    Please help us urgently.

  • 0 in reply to Roberto Benevelli
    Prodigy 20 points

    We found the problem: it was in facts a wrong reading mechanism of the ADC 16 bit values stored in the FPGA through an 8 bit bus of the microprocessor.
    No issue for ADS8689