ADS7028: RMS computation sampling frequency and conversions

Hi Joel,

Okay, thanks for confirming! Manually triggering each RMS sample is burdensome given our firmware implementation so we may explore other ADC hardware options. Does TI have any comparable ADCs with a SPI interface that does support RMS computations based on internally triggered samples?

Also, I think the ADS7028's datasheet should be updated or errata published to reflect that the RMS module requires manual triggering for each sample. We likely would not have chosen the part for our design had we known this limitation.

Hi Joel,

I've been running further tests with the ADS7028 to see how we could best accommodate the manual triggering requirement for RMS sampling if we do end up keeping the part in the design. Is there a known max RMS sampling frequency? I originally thought it would be 1Mhz as specified by the datasheet, but I haven't been able to manually trigger RMS samples at nearly that speed and still have the RMS module successfully complete an RMS measurement in the expected observation window given the configured RMS sample count.

My testing shows that the maximum RMS sampling frequency (i.e. the fastest I can manually trigger RMS samples and still have a successful RMS computation) is somewhere between 7kHz and 8kHz. I have the ADS7028 in the default Manual Mode, I am manually triggering RMS samples by toggling the CS line via a timer, and it doesn't matter which RMS sample count I configure the ADS7028 with (1024, 4096, 16384, or 65536).

Hi Nicholas,

1MSPS is the max frequency that the ADC can achieve. Since the RMS_SAMPLES field minimum requires at least 1024 samples to compute the RMS, the maximum "RMS frequency" is less than 1ksps on the ADS7028.

Can you share some logic analyzer captures on how you are triggering the manual conversions? What SCLK frequency are you using?

It could also be that the analog front end circuit is not adequate for the input signal you are trying to compute the RMS of, and you are seeing a settling error if you try to sample quickly. Are you able to share a schematic?

At the moment I only have hardware for the ADS7128 and ADS7038 devices. I can order some ADS7028 devices and try to share a sequence that might work.

Regards,
Joel

Hi Joel,
I am triggering the manual conversions by simply toggling the CS line low and high at a fixed rate. Table 8 in ADS7028's datasheet shows that conversions are controlled by the rising edge of the CS line when in Manual mode. I understand that the maximum achievable RMS measurement rate is affected by the configured number of RMS samples and will therefore not be 1MHz, but what I'm seeing is that the maximum sample rate for the RMS samples themselves is much less than 1MHz (I find it to be somewhere between 7kHz and 8kHz). The signal being sampled is only 60Hz so a really high RMS sampling rate is not necessarily needed, but I would like to know what the maximum achievable RMS sampling rate is so that we can properly maximize our RMS sample count while still fitting within our desired observation window.

Here's a rough outline of how I tested for the maxium possible RMS sampling rate:
1. Configure the ADS7028 for 1024 RMS samples and begin the RMS measurement
2. Toggle the CS line low and high at a fixed rate (this is done using one of the host micro's timers)
3. Wait for 1050 CS periods (the amount of time depends on the previously configured CS frequency, and an extra 26 periods are added for overage)
4. Stop toggling the CS line
5. Read back the ADS7028's SYSTEM_STATUS register and check if the RMS_DONE bit is set

I verified using an oscilloscope that there are a minimum of 1050 CS periods between steps 2 and 4, and the RMS_DONE bit is always set at step 5 as long as the CS frequency is set to less than ~7.2kHz in step 2. Note that I'm also power cycling the ADS7028 between tests.

I'm also only concerned with the ADC's RMS behavior right now and not yet with our hardware's accuracy, but I'll send over schematics if that changes.

Hi Nicholas,

I should be getting hardware this week to help verify. In the meanwhile, do you have any logic captures to share on the sequence you are executing? This would help me verify the sequence and timings, in case there are any obvious issues that might be limiting the effective sampling speed. 

I should be able to clarify more of the operation with my setup. I will keep you updated on the status. Unfortunately I only have the ADS7128 on hand, not the ADS7028. 

Regards,
Joel

Hi Joel,

Here's the sequence of commands that I'm sending to the ADS7028 for a successful RMS computation (note: clock frequency is 750kHz).

Configure RMS settings (DC component subtraction enabled, 1024 RMS samples, channel 0):

Clear the RMS_EN bit in the GENERAL_CFG register:

Start the RMS computation by setting the RMS_EN bit in the GENERAL_CFG register:

Toggle the CS# line at 7kHz, 50% duty cycle for 150ms:

Read back the SYSTEM_STATUS register to confirm that the RMS computation completed:

If I follow the same sequence but with toggling the CS# line at a faster rate and for a proportionally shorter amount of time (e.g. 10kHz for 105ms) then the RMS computation does not finish despite seemingly enough manually triggered RMS samples. And note that the RMS sample count, CS# line toggle frequency, and CS# line toggle duration shown here is not reflective of the final observation window we would use for the 60Hz signal we’re measuring; these are all just settings I’ve been testing with to better understand the RMS computation behavior.

Hi Nicholas,

Sorry for the delay on this issue. I'm still waiting on units. It seems like they just got shipped today, so I will keep you updated on the status. I'm not too confident in trying to debug your issues without hardware in hand, especially since there have been inconsistencies with this family in trying to implement what is described in the datasheet.

Regards,
Joel-

Hi Joel,

Okay, no worries! Thanks for the continued support and communication.

Hi Joel,

Another issue I just ran into with this ADC: I cannot successfully complete an RMS computation on any channel other than channel 0. If I try the same sequence of commands as I gave before but with RMS_CHID within the RMS_CFG register set to some value other than 0 then the RMS computation never finishes (as evident by reading back the SYSTEM_STATUS register). Can you confirm the same behavior on your end once you receive the ADS7028 hardware?

Hi Nicholas,

Will do. I've had another customer with a similar issue, so I need to test to clear this up once and for all. Thank you for your patience here.

Regards,
Joel