AFE5832LP: configure PLL

Hi, 

TX_TRIG signal can be used to align the phase of 32 channels. Frequency of TX_TRIG signal should be a multiple of Fs/2

could you please give me a protocol that I should follow or pieces of example codes which should help me a lot to quickly solve the problem. Thank you very much. qi

Hi, after initializing the device after power up as recommended in datasheet section 10.4, TX_TRIG signal can be given such that the width of TX_TRIG pulse is atleast Fs/2 where Fs is system clock. 

Hi could you please tell me after I configured PLL +TX_TRIG for initiation stage, what should I do to avoid phase influences of TX_TRIG on sampling? in dataseet, I found "The phase reset from TX_TRIG can be disabled using MASK_TX_TRIG”(8.3.10.2 ADC Synchronization Using TX_TRIG), but the datasheet does not tell me how to perform this and also there is no MASK_TX_TRIG at all in the datasheet. "

Many thanks,

Qi

MASK_TX_TRIG bit is in address 46h, bit <2>