We have sinusoidal signal w.r.t 2.50V.This signal is always w.r.t. 2.50V.We fed this signal to ADS1256 ADC chip from TI which is configure with 2.5V reference on pin 4 as per data sheet page no.28 guideline.
Test 1:
1: Input: 5Vpp with 2.5V reference on channel AIN0 and 0V on AIN1
2: PGA = 1
3: Configuration: Differential Mode for AIN0+ and AIN1-
Report:
Output is as per requirement and signal is 1:1 as PGA = 1
Test 2:
1: Input: 2.5Vpp with 2.5V reference on channel AIN0 and 0V on AIN1
2: PGA = 2
3: Configuration: Differential Mode for AIN0+ and AIN1-
Report:
Output is saturated to full scale as PGA = 2
Test 3:
1: Input: 1.25Vpp with 2.5V reference on channel AIN0 and 0V on AIN1
2: PGA = 4
3: Configuration: Differential Mode for AIN0+ and AIN1-
Report:
Output is saturated to full scale as PGA = 4
We can clearly conclude that PGA also amplify dc shifting.We need output which always give proper signal without clip even though input is always w.r.t +2.5V.To resolve this issue we given voltage between 0V and 2.50V on AIN1-.This gives us result to some extent for given PGA >= 2 setting.I think this is difficult in any practice application to provide some finite voltage on AIN-.Please suggest us to simplify this solution.
-
Ask a related question
What is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
