ADC3563: Channel B Test Pattern

Hi Ali,

You are using an ADC3563, which is a single channel device. Channel A is enabled, and Channel B is disabled. Why are you wanting to capture a test pattern on the channel B lanes?

Best,

Luke Allen

Hi Luke,

Hi Ali,

Ah, I see. Thank you for clarifying. Unfortunately, I don't have an EVM for a single channel device here in the lab to verify this, but I believe you need to enable the DB0 and DB1 lanes manually. For the single channel devices, these lanes are disabled by default to save power. You can enable them by writing 0 to the PDN_DB0 and PDN_DB1 fields in register 0x09.

Please give this a try and let me know if you are still seeing the issue.

Best,

Luke Allen

Hi Luke,

 I write to the registers in the following order. The problem continues. However I observed that every now and then both da0/da1 and db0/db1  output test pattern. But it is very rare.

[ADC1] REG_SW_RESET (0x0000) -> 0x01 (rb=0x00)

wait 300 ms
[ADC1] REG_OP_IF_MAPPER (0x0007) -> 0x4B (rb=0x4B)  (rb: read back)
[ADC1] REG_EFUSE_LOAD (0x0013) -> 0x01 (rb=0x00)
[ADC1] REG_BIT_MAPPER (0x001B) -> 0x88 (rb=0x88)
[ADC1] REG_DIG_FEATURES (0x0024) -> 0x0E (rb=0x0E)
[ADC1] REG_DECIM (0x0025) -> 0xD0 (rb=0xD0)
[ADC1] REG_OP_ORDER_A (0x0027) -> 0x10 (rb=0x10)
[ADC1] REG_OP_ORDER_B (0x002E) -> 0x10 (rb=0x10)
[ADC1] REG_FCLK_CTRL (0x0019) -> 0x80 (rb=0x80)
[ADC1] REG_NCOA_FTW0 (0x002A) -> 0x00D35590 (rb=0x3F507507)
[ADC1] REG_NCOB_FTW0 (0x0031) -> 0x00D4DC30 (rb=0x3FC57C58)
[ADC1] REG_MIX_CTRL (0x0026) -> 0x88 (rb=0x88)
[ADC1] REG_MIX_CTRL read 0x88
[ADC1] REG_MIX_CTRL (0x0026) <- 0xAA (assert)
[ADC1] REG_MIX_CTRL (0x0026) <- 0x88 (clear)
[ADC1] REG_OUTBUF_PDN (0x0009) -> 0x00 (rb=0x00)

is software reset alternative to hardware initialization?

I connected REFBUF pi to ground thru 0.1 uF capacitor. Could this be the source of the problem?

Regards,

Ali Tevfik Dengizek

Hi Ali,

Can you explain what you mean when you say you "observed that every now and then both da0/da1 and db0/db1  output test pattern" Does this mean intermittently while the ADC is running, after power cycling, etc?

Can you calrify your question "is software reset alternative to hardware initialization?" Once the part is brought up, you can use either the hardware reset pin or the software reset register to reset the part. This does not exempt you from following the correct bringup sequence described in the datasheet.

Yes, this is likely an issue, although I am not sure it is the cause of your problem. Puling the REFBUF pin low configures the ADC to use a single ended clock input.

Best,

Luke Allen

Hi Luke

It rarely works after power cycling. I pulled the REFBUF pin to AVDD. It did not help.

Regards,

Ali Tevfik Dengizek

Hi Ali,

Can you please provide a bit more information so I know exactly what you are trying. Are you:

1. Powering up the device

2. Programming the above register config

3. Observing the correct output

4. Power cycling

5. Reprogramming the above register config

6. Observing the incorrect output

Please let me know if this is correct

Best,

Luke Allen

Hi Luke,

Yes.  It is correct.

Regards,

Ali Tevfik Dengizek

Ali,

Thanks for clarifying. A few more questions:

1. When you power cycle the device, are you following the initialization sequence outlined in section 9.2 of the ADC3563 datasheet?

2. When you experience the "incorrect" output, are you seeing the CHB outputs being held high, as shown in your previously attached timing diagram?

3. Are you experiencing this on both ADCs? Or have you only tested on one ADC.

4. Would it be possible to share your schematic with us? We can move this discussion to an email if you'd prefer.

Best,

Luke Allen

Hi Luke,

Following is the sequence of programming the registers: 

   Register                            Address   Value   Comments
1 REG_SW_RESET           0x0000     0x01     Soft reset
   wait 30 ms
2 REG_OP_IF_MAPPER   0x0007    0x4B      2-wire, 16-bit, mapper enable
3 REG_EFUSE_LOAD       0x0013    0x01      eFuse 
   wait 30 ms
4 REG_EFUSE_LOAD       0x0013    0x00      eFuse Clear 
5 REG_FCLK_CTRL          0x0019    0x80      FCLK source = DDC
6 REG_BIT_MAPPER        0x001B   0x88      Bit-mapper enable + 16-bit mode
7 REG_DIG_FEATURES   0x0024    0x0E      Enable DDC, bypass filters, A→AB
8 REG_DECIM                   0x0025    0xD0     Decimation-by-32 + DDC mux enable
9 REG_OP_ORDER_A      0x0027    0x10      Output Q,I order (A)
10 REG_OP_ORDER_B    0x002E    0x10      Output Q,I order (B)
11 REG_NCOA_FTW0       0x002A    FTW(A) 32-bit NCO-A frequency tuning word
12 REG_NCOB_FTW0       0x0031    FTW(B) 32-bit NCO-B frequency tuning word
13 REG_MIX_CTRL           0x0026    0x88      Mixer gain +6 dB (A & B)
14 REG_MIX_CTRL           0x0026    0xAA
15 REG_MIX_CTRL           0x0026    0x88
16 REG_REF_CTRL          0x000E    0x8C     External reference + PDN/SYNC→SYNC
17 REG_OUTBUF_PDN    0x0009    0x00      Output buffers enabled

I verify the programmed register values by reading back. 

Regards,

Ali Tevfik Dengizek

Hi Ali,

That is understood. Your register configuration looks correct, but I was not asking about your register configuration. Please re-read my previous post.

Best,

Luke Allen

Hi Luke,

1. No, I am not following the initialization sequence given in section 9.2. I assumed that performing a soft reset would be sufficient.

2. For the second ADC, one of the DB outputs is held high and the other is held low.

3. Yes, I am observing this behavior on both ADCs.

4. I think it would be better to move this discussion to email. My email address is ali.dengizek@iewtech.com. If you share your email address with me, I can send you the schematic.

Regards,
Ali Tefik Dengizek

Hi Ali,

Thank you for clarifying. I am going to close this post and reach out via email.

Best,

Luke Allen