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ADC3563: Channel B Test Pattern

Ali Tevfik Dengizek
Prodigy 20 points
Part Number: ADC3563


Hi,

I have two ADC3563  on the same board. I configure them to emit constant test pattern (0x0CC0)  but neither of two ADCs output correct custom constant pattern on B channel.   

I configure the ADC registers in the following order (as suggested in the datasheet and in the answer to a similar problem in this forum): 

[ADC1] REG_SW_RESET (0x0000) -> 0x01  (rb=0x00)
[ADC1] REG_OP_IF_MAPPER (0x0007) -> 0x4B  (rb=0x4B)
[ADC1] REG_EFUSE_LOAD (0x0013) -> 0x01  (rb=0x00)
[ADC1] REG_BIT_MAPPER (0x001B) -> 0x88  (rb=0x88)
[ADC1] REG_DIG_FEATURES (0x0024) -> 0x0E  (rb=0x0E)
[ADC1] REG_DECIM (0x0025) -> 0xD0  (rb=0xD0)
[ADC1] REG_OP_ORDER_A (0x0027) -> 0x10  (rb=0x10)
[ADC1] REG_OP_ORDER_B (0x002E) -> 0x10  (rb=0x10)
[ADC1] REG_FCLK_CTRL (0x0019) -> 0x80  (rb=0x80)
[ADC1] REG_NCOA_FTW0 (0x002A) -> 0x3F507507  (rb=0x3F507507)
[ADC1] REG_NCOB_FTW0 (0x0031) -> 0x3FC57C58  (rb=0x3FC57C58)
[ADC1] REG_MIX_CTRL read 0x88
[ADC1] REG_MIX_CTRL (0x0026) <- 0xAA (assert)
[ADC1] REG_MIX_CTRL (0x0026) <- 0x88 (clear)


[ADC1] REG_CUSTOM0 (0x0014) <- 0x00 readback = 0x00
[ADC1] REG_CUSTOM1 (0x0015) <- 0x33 readback = 0x33
[ADC1] REG_CUSTOM2 (0x0016) <- 0x6C readback = 0x6C

Following is the data capture screen shot.:

The first ten signals belong to ADC-1,  and the following signals belong to ADC-2. 

 sig_mon_5/6 and sig_mon_11/12 are the b channel of ADC1 and ADC2.  

ADC Screen Shot-01.png
What could be the possible causes of this problem?   

Regards,

Ali Tevfik Dengizek 

 

  • 0
    TI__Intellectual 2100 points

    Hi Ali,

    You are using an ADC3563, which is a single channel device. Channel A is enabled, and Channel B is disabled. Why are you wanting to capture a test pattern on the channel B lanes?

    Best,

    Luke Allen

  • 0
    Prodigy 20 points

    Hi Luke,

    Thanks for sparing your time to help me with the issue. Sorry for not being  very clear. What I meant by chanel B was actually  DDCB. I configured DDC MUX in register 0x24 as 0x01. This setting directs Channel A to DDC A and DDC B.  I expect that when both TEST PAT A and TEST PAT B in register 0x14 are set to constant pattern (011),  pattern programmed in 0x14,0x15,0x16 will be output in both DA0/DA1 and DB0/DB1 lanes. I see the pattern  only at DA0/DA1 lanes.  
    Regards,
    Ali Tevfik Dengizek
  • 0 in reply to Ali Tevfik Dengizek
    TI__Intellectual 2100 points

    Hi Ali,

    Ah, I see. Thank you for clarifying. Unfortunately, I don't have an EVM for a single channel device here in the lab to verify this, but I believe you need to enable the DB0 and DB1 lanes manually. For the single channel devices, these lanes are disabled by default to save power. You can enable them by writing 0 to the PDN_DB0 and PDN_DB1 fields in register 0x09.

    Please give this a try and let me know if you are still seeing the issue.

    Best,

    Luke Allen

  • 0 in reply to Luke Allen
    Prodigy 20 points

    Hi Luke,

     I write to the registers in the following order. The problem continues. However I observed that every now and then both da0/da1 and db0/db1  output test pattern. But it is very rare.

    [ADC1] REG_SW_RESET (0x0000) -> 0x01 (rb=0x00)

    wait 300 ms
    [ADC1] REG_OP_IF_MAPPER (0x0007) -> 0x4B (rb=0x4B)  (rb: read back)
    [ADC1] REG_EFUSE_LOAD (0x0013) -> 0x01 (rb=0x00)
    [ADC1] REG_BIT_MAPPER (0x001B) -> 0x88 (rb=0x88)
    [ADC1] REG_DIG_FEATURES (0x0024) -> 0x0E (rb=0x0E)
    [ADC1] REG_DECIM (0x0025) -> 0xD0 (rb=0xD0)
    [ADC1] REG_OP_ORDER_A (0x0027) -> 0x10 (rb=0x10)
    [ADC1] REG_OP_ORDER_B (0x002E) -> 0x10 (rb=0x10)
    [ADC1] REG_FCLK_CTRL (0x0019) -> 0x80 (rb=0x80)
    [ADC1] REG_NCOA_FTW0 (0x002A) -> 0x00D35590 (rb=0x3F507507)
    [ADC1] REG_NCOB_FTW0 (0x0031) -> 0x00D4DC30 (rb=0x3FC57C58)
    [ADC1] REG_MIX_CTRL (0x0026) -> 0x88 (rb=0x88)
    [ADC1] REG_MIX_CTRL read 0x88
    [ADC1] REG_MIX_CTRL (0x0026) <- 0xAA (assert)
    [ADC1] REG_MIX_CTRL (0x0026) <- 0x88 (clear)
    [ADC1] REG_OUTBUF_PDN (0x0009) -> 0x00 (rb=0x00)

    is software reset alternative to hardware initialization?

    I connected REFBUF pi to ground thru 0.1 uF capacitor. Could this be the source of the problem?

    Regards,

    Ali Tevfik Dengizek