Problems with ADC ADS5463

Hi,

i cannot tell much from what you have said so far.  I presume the top plot is an oscilloscope screenshot of the input?  Is that a from a differenital probe or a single ended shot of one side of the differential input?  What is the common mode level of the signal - that is, if the signal is symmetrical about some voltage, what is that voltage?  I can't really tell much about what your input signal really looks like yet.

You mention AVDD = 3.3V, but there is a 5V analog supply and a 3.3V analog supply.  Do you have 5V for the AVDD5 and 3.3V for the AVDD3?

The DRY signal out can be used as a DDR (dual data rate) clock into the FPGA, but notice in the data sheet that the DRY edges are aligned with the transitions of the data bits, so the the DRY signal must be delayed by 90 degrees to put the edges of the DRY signal centered on the valid portion of the data to meet setup and hold time.  Also - samples are present on the rising *and* falling edges, so you would want to use something like the IDDR cell that Xilinx provides.  Attached is a block diagram on how we latch data from the ADS5463 into the Virtex4 of the TSW1200.  In that sketch, a bank of 12 IDDR cells catch the DDR data, outputting a rising edge sample and a falling edge sample.  The IDELAY cell allows for delay taps to be set to meet timing into the IDDR cell.

Regards,

Richard P.

Hello, Richard.

Sorry for my bad English.

Yes, the first picture is a picture with an oscilloscope, the second pictute from Matcad. Yes, Richard. At the entrance of the ADC is saw (wedge), simple meander, amplified by differential amplifier. The file recorded from Virtex-4 on a PC. Frequency of 4.0625 Mhz, meandering 16 times less than the sampling frequency. If you lodge noise on the input, the average is equal to 250 units. Signal voltage VREF = the symmetrical 2.4 V, there is no offset.

Yes of course.  I forgot to mention. In the scheme there are voltage AVCC = 5 V.

Thanks for the recommendations. But the implementation is not provided.

Post two file data.

Thanks, Richard!

Positive edge DRY

0066.signal1.txt

Negative edge DRY

0020.signal2.txt

Hi,

i still do not know what you want the sample data to look like because i do not know what your input signal looks like.  That oscilloscope display looks like an envelope of a waveform, and i don't know if i am looking at a waveform from a differential probe or one side of the differential signal, or what the common mode level of the signal is. 

You say VREF is 2.4V - are you using internal or external refernece?  Is that 2.4V something you measure from the device or something you are applying to the device?  If you use external reference then changing VREF will change the full scale definition of the device.  If you are using internal reference then this pin outputs 2.4V and you get default full scale definition.  It so happens that the differential input signal should have a common mode level of 2.4V adn you can use this VREF to bias the signal swing around 2.4V, but that biasing doesn't happen in the DC-coupled case unless you do the biasing.  If the amp has a common mode input then you can use VREF to bias the amp output to 2.4V.  If your input signal is AC coupled then Figure 57 of the datasheet shows that the signal will automatically be biased to 2.4V by the two 1000ohm biasing resistors in the input structure.  What is the common mode level of your inptu signal?

i attached a block diagram of how we implement an FPGA interface to this ADC in a Virtex4.  I see that gif displayed inline with my reply.  Do you not see that?

Regards.

Richard P.

Hello!

If all simplify.  Simple signal real-time component Vin = +1.8 V and Vin = -1.8 V. Voltage 1.8-1859 code (OpCode), voltage-1.8 v-code -1183. As with any input voltage is constant only measurement error.

2806.signal5.txt

VREF = 2.4 in internal voltage measured at contact VREF (PIN6). The voltage is measured in the ADC. Richard, I use this signal to offset, do everything as in ADS5463.pdf.

I have seen this file *.gif, I implemented this scheme. Virtex is working correctly and grab the correct data. Implementation of TSW1200_LVDS_DDR or another gives one result.Richard, likely something with the chip.

Please send file, where there is a figure 57. I can't find.

Thank you!

Hi,

Figure 57 is in the datasheet, page 31.  It just shows that if you AC couple the input signal then we will bias the signal to the desired common mode voltage.  Is your signal from the amp AC coupled?  or do you use VREF to the common mode input of the amp to bias the signal to the desired common mode?

What are all the numbers in the .txt file supposed to mean?  I do not know what the problem is that you are trying to describe.  i don't need to know what the signal looks like anywhere but at the input pins of the ADC when I ask what the common mode level of your input is.  You say Vin = +1.8V and Vin = -1.8V.  where is that measured?  I hope it is not at the input to the ADS5463.  The input to the ADS5463 needs to be a differential signal with peak to peak amplitude of less than 2.2V and centered about 2.4V.  So if the voltage at the AIN pin is 1.85V while the voltage at the /AIN pin is 2.95V then the output code would be 0000 0000 0000 because the voltage across the inputs would be -1.1V.  If the voltage at the AIN pin is 2.95V while the voltage at the /AIN pin is 1.85V then the output code would be 1111 1111 1111 because the voltage across the inputs would be +1.1V.   If the voltage across AIN and /AIN is greater than +1.1V  or -1.1V at any time then the outptu will clip to positive or negative full scale.  if the voltage across the input is less than 1.1V but not centered about 2.4V then there could be performance degradation or even incorrect output.  Does your input signal to the ADA5463 fit within these guidelines?

Regards,

Richard P.

Hello!

Richard, I'm confused. No, my signal is coming from the amplifier (PGA870) ADC, VREF power connection is not. I tried to link the VREF with flat bar filter. The result is missing. In txt file values corresponding to the differential input voltage VIN = +/-560 mV. Tentatively translated code was transferred to the additional code. +560 mV is 1860, but should be around 1180.  -560 value corresponds to the value -1180 and rightly so. VIN = +/-1.8 V voltage between VIN and GND, my mistake. Richard, all right, the signal fits. I have this monitor using the amplifier. I think the problem inside the chip, in the input chain, namely protection diodes. Very little resistance between ~VIN and GND. I am checking.

Sincerely, Vladimir!

I still have no idea where you are measuring +/-1.8V and there is nothing around the ADS5463 that should be described in terms of +/-1.8V.    That is larger than the full scale range of the ADS5463.

If the values in that txt file you attached are supposed to represent the codes out of the ADC when the input has a -560mV differential voltage across the analog input pins, then what is the absolute voltage on the AIN pin relative to ground and what is the absolute voltage on the /AIN pin relative to ground at that time?  if you have an input signal across the analog inputs that is -560mV differential, then the volage at AIN would have to be 2.12V while the voltage at /AIN would have to be 2.68V in order for a -560mV differential signal to have the proper common mode.   

I did not see any value in that txt file that was not around the value -1180 so I expect this file represents a single input voltage sampled many times.  Also, the output format of the ADC is offset binary and not two's complement so i expect you did some conversion to the captured data to represent it as -1180.  What were the actual bit codes?

Regards,

Richard P.

Hello!

Richard, see ABSOLUTE MAXIMUM RATINGS table. The data in the file cannot be represented in the additional code I wrote. The main question remained unanswered, where offset in code.  Possible, all linked with VCM.

 Sincerely, Vladimir!

Hi,

What do you wish me to look at in the absolute maximum ratings table?  This table is only to set limits before permanent damage to the device might occur.  This table does not imply anything about operating conditions.    For example, in recommended operating conditions the full scale input is listed as 2.2V peak to peak differential.  if you exceed the recommended operating value then you may see clipping in the output but not damage to the device.  if you exceed the absolute maximum limit on AIN to /AIN then there may eventually be damage to the device.   Don't exceed the absolute maximum limits, and if you wish to see proper behavior of the device then don'e exceed recommended operating conditions either. 

I do not understand what you mean by the rest of the posting about 'cannot be represented in the additional code' or the 'offset in code'.   I do suspect that the signal out of your amp and into the data converter is not set up to match the requirements of the data converter, either the common mode level of the signal or the amplitude of the signal - but I can't tell from the information provided.  That is why I try to take the information I do see provided in your postings and I ask very specific questions about the data but I don't see answers to those questions. 

Regards,

Richard P.