Part Number: ADS9817
Dear team,
During the use of ADS9817, it has been able to collect data correctly without any changes in the FPGA firmware, upper computer software, or hardware. However, there may be sudden anomalies in the data collected by individual ADCs during use. The abnormal state occurs in four consecutive channels, that is, all 1-4 or 5-8 channels of an ADC have inaccurate data collection, and when the same voltage/current is set, the abnormal results of the ADC's 1-4 or 5-8 channels are basically the same. Once this abnormality occurs irreversibly, it can be reset by powering on again, and the same abnormal state still occurs. If the abnormal ADC module of the board is replaced, the updated ADC module can collect data normally.
For example, in the following abnormal situation, setting the full channel voltage to 1.5V, the collection of channels 0-15 is normal, while channels 16-19 and 20-23 have abnormal collection. After 24 channels, normal collection can also be achieved. At the beginning, the 8 abnormal channels were able to work normally, and there were no changes in the FPGA firmware, upper computer software, or hardware. However, during continuous testing, this abnormality occurred, and the abnormal ADC chip was observed to be slightly higher than other ADCs by a temperature gun. (The display from 16 to 19 shows 0V, but when directly capturing the observation from D3, the highest bit is 1, indicating that the ADC has collected a negative value and the upper computer displays 0.)
In terms of ADC configuration, SPI clock transmission rate is 10M, using binary complement code and 2-channel DDR CMOS data interface method, fSMPL_CLK = 4MHz,The data clock frequency for interface mode is 48M. Follow the steps below to initialize the sequence and configure relevant information.
After power on, when no parameters are set, the correct channel output acquisition results for D1 and D3 are about 1520, and the subsequent voltage needs to be converted to basically 0V:
After power on, when no parameters are set, the abnormal channels D1 and D3 output the collection results, with the highest bit being 1, and the data is clearly abnormal:
Set 1.5V, D1, D3 to output the collection results correctly through channels:
Set 1.5V, abnormal channels D1 and D3 output collection results, obviously inconsistent:
The other abnormal phenomenon of channels 52-55 is as follows (the highest bit is 1, which means the ADC collects negative values and the upper computer displays 0):
After power on, when no parameters are set, channels D1 and D3 output the acquisition results, with D3 outputting normally and D1 outputting abnormally:
Set 1.5V, abnormal channels D1 and D3 output the collection results, with D3 outputting normally and D1 outputting abnormally:
After replacing the abnormal ADC with a new one, the abnormal channel can collect data normally.
