Part Number: ADC3443
Hi Team,
Posting on behalf of our customer.
I have a question about how to achieve synchronization among multiple ADC3443 devices. There are four devices on the board. In the datasheet of ADC3443, the sysref pin can be used to synchronize the sample clock, can we use this pin to achieve synchronization ? if this pin can be applied , does it must be use when the clock-divider feature is used? how to ensure that the output data of channels are aligned.
Does it must be using divided clock ,when using SYSREF to achieve synchronization among multiple devices?
As the figure show, SYSREFP,SYSREFM pin are connected to FPGA, what voltage level is the fpga diff output pin configured to?
the same question for DCLKP/M , FCLKP/M pin.
Regards,
Danilo
