ADS 5474 and DAC5682Z

Hi, Matt Guibord,

Thanks for your kind help in the past. Now I use the ADS 5474 to sample an audio signal, and then the sample data are processed by FPGA, and finally output by the DAC 5682Z. THe ADS 5474 runs at 400MSPS. If the sample data are not processed , and directly transferred to the DAC, the system works correctly. But if they are processed by the FPGA, and then output by the DAC, the system does not work correctly. There are high-frequency noises in the output waveform. From real-time tracing, I found that the sample data are input into the FPGA, and processed by the FPGA. And I also verify the processing algorithm is correct. For example, I stored the sample data into a block RAM inside FPGA, and read it into the processing module, and finally send the processed results to the DAC, the system works well. Could you mind give me some advices how to debug the system?

Thanks,

Steven

Hi Steven,

If the system works when you pass data straight from the ADS5474 to the DAC5682z, but doesn't when you include the algorithm, you have to think that there is something in the algorithm that's at fault... The DAC and ADC setup shouldn't be changing between the two setups. Did you make sure the DAC5682z DLL is locked? High-frequency noise (like a glitch) could be caused by timing problems. Does the FPGA interface to the DAC5682z change at all between the two setups?

It would be helpful if you could send some plots of what you're seeing.

Regards,
Matt Guibord 

Hi, Matt,

Thanks for your reply. I think our algorithm has no problem, because when I store data into a block ROM inside FPGA, and then the algorithm read the data and carries out calculation, the calculation results is finally sent to the DAC board. From the external osilloscope. I can watch the correct calculation results. When I input data from A/D board, the system can not work correctly. I adout the input data from A/D is not correct.  Today, I do not add our algorithm in the system. And a sine wave generated by a function generator is input into the AD board, and then the sampled data are transferred to the D/A board. The waveform displayed on the ossilloscope is attached. From the

Steven,

Based on this description, it sounds like there is a problem with the ADC to FPGA interface. Can you verify your four test cases below?

1. When the ADC data is put into the RAM and readout, the data is incorrect (has glitches?)

2. When the ADC data is put through the algorithm and output through the DAC, the data is still incorrect (does the DAC output have the same glitches seen in case 1?)

3. When good data is put into RAM and output through the DAC, the output is fine.

4. When good data is put into RAM, put through the algorithm, and output through the DAC, the output is still fine.

Thanks,
Matt Guibord 

Hi, Matt,

Thanks for your reply. I have tested the case2, case 3, and 4. The DAC works fine in case 3 and case4.  In case 2, the output of DAC includes high frequency noise. Thus I adout the ADC input contains noise. If it does,  how to handle it in the ADC to FPGA interface? I will test the case 1.  Typically, how to reduce the noise from the ADC?

Thanks

steven

Hi Steven,

I believe this is a timing error with the ADC, not actual noise from the ADC. You'll need to check your timing constraints of your FPGA.

Regards,
Matt Guibord