ADC3542: External Clock Generation

Hello,

I am considering using the ADC3542 with an FPGA to acquire data from a thermal sensor. The datasheet states that, to maximize ADC SNR performance, the external sampling clock should have low jitter and use differential signaling with a high slew rate.

After consulting with the FPGA vendor, they advised against using the FPGA’s internal PLL to generate the ADC clocks due to concerns regarding jitter and precision. Could you recommend an external IC suitable for generating the required clock signals for the ADC?

The sensor provides the input clock, and the required outputs are:

• A clock signal at the same frequency as the input, with a 90° phase shift, for the CLK signal.

• A second clock signal, 8 times the input frequency, for the DCLK signal.

Additionally, is it possible to use the 1-wire serial interface in 16-bit mode? If so, do I need to change the register address from 0x07 to 0x6C and set registers 0x1B to 0x88?

Thank you for your support.

EDIT: The t_PD is defined as the time from the sampling clock falling edge to the DCLK rising edge; however, for the 1-wire serial interface, this is not reflected in the timing diagram. Should the reference edge be the falling edge only for this interface? Also, is the t_PD value still defined as 2 + t_DCLK + t_CDCLK for t_CDCLK < 2.5 ns, and 3 + t_CDCLK for t_CDCLK ≥ 2.5 ns?