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ADS1256: software calibration strategy to maximize throughput in multiplexing

Renan Santos Adriano
Mastermind 26215 points

Part Number: ADS1256
Other Parts Discussed in Thread: ADS1261

Hello Experts,

I am designing a multichannel data acquisition system using the ADS1256. The application requires frequent switching of the input MUX, PGA settings, and Data Rates.

Running a hardware self-calibration (SELFCAL) after every change in MUX/PGA configuration introduces a significant latency (up to ~1s depending on DRATE), which is unacceptable for my target system throughput.

To maintain high throughput while keeping high accuracy, I am planning to implement a software calibration strategy. I would appreciate your feedback on whether this approach is valid.

Here is the workflow:

  1. Characterization: The MCU cycles through all necessary MUX/PGA/DRATE combinations. For each config, it runs SELFCAL, reads the resulting OFC and FSC register values, and stores them in a lookup table in the MCU RAM.

  2. Acquisition: During normal operation, I write "Ideal" values to the ADC registers (OFC = 0 and FSC = IDEAL FSC from datasheet Table 18). This allows switching MUX/PGA instantly without waiting for calibration. The ADC outputs "Uncalibrated Data".

  3. Compensation: The MCU applies a linear correction to the uncalibrated data using the stored OFC/FSC values.

Based on the ADS1256 architecture (Figure 23 of the datasheet and equation 3), I derived the following compensation formula to be calculated by the MCU:

Final_Output = FSC/Ideal_FSC*(Raw_Output - OFC/alpha*Ideal_FSC*beta)

Where:

  • FSC and OFC: The stored real calibration values.

  • Ideal_FSC, Alpha, Beta: Coefficients from Datasheet Table 18.

Here are my questions:

  • Is this mathematical model correct for the ADS1256 internal ALU processing path?
  • Are there any hidden pitfalls in driving the ADS1256 with fixed "ideal" calibration registers while handling the calibration correction externally?

Thanks in advance for your support.

Alessandro

  • 0
    TI__Guru 58951 points

    Hi Renan Santos Adriano,

    Can you please have the customer post their questions directly in the e2e forum using their company email address, instead of going through CSC?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 30 points

    Thank you Bryan, I signed to the e2e forum with my company email. Regards, Alessandro

  • 0 in reply to Alessandro di Bona
    TI__Guru 58951 points

    Hi Alessandro di Bona

    Thanks for following up on this

    The procedure you described should work fine, you are just taking the calibration from inside the ADC to inside your controller code

    You mentioned you will include every "mux" combination, which should not be necessary unless you are trying to calibrate your system external to the ADC e.g. any additional signal conditioning circuitry you have placed before the ADC. The internal calibration disconnects the buffer/PGA/ADC inputs from the mux output, so there is no benefit in trying to calibrate the different mux channels. You should however calibrate based on whether the buffer is enabled / disabled

    You can also consider using something like the ADS1261, which is effectively the next generation version of the ADS1256. This device does not have alpha / beta values that are different for different data rates, so it will be a little simpler to calibrate. However, the ADS1261 VREF voltage is not routed to the inputs for the gain calibration either like it is using the ADS1256, you would manually need to route the VREF voltage to one of the inputs to accomplish this.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 30 points

    Hi Bryan,

    Thank you for the clarification. It is very helpful to know that the MUX is physically disconnected during the internal calibration.

    However, my application requires switching not only the MUX but also the PGA Gain dynamically between channels to handle different signal ranges.

    My understanding is that while the MUX setting is irrelevant for SELFCAL, the PGA (and Buffer) settings are part of the calibrated path. Therefore, the Offset (OFC) and Full-Scale (FSC) values will change significantly if I switch the Gain (e.g., from 1V/V to 64V/V).

    To avoid the latency of running a hardware SELFCAL every time the Gain changes, I still plan to use the Look-Up Table approach to store and mathematically apply the specific OFC/FSC values for each PGA configuration used in my scanning sequence.

    Could you please confirm that this is the correct strategy to handle dynamic PGA switching without throughput penalties?

    Thanks again, Alessandro

  • 0 in reply to Alessandro di Bona
    TI__Guru 58951 points

    Hi Alessandro di Bona,

    My only comment was about the mux configuration being irrelevant to the calibration coefficients, while the buffer configuration is important. However, I could have explicitly state that yes the PGA gain and data rate are also important. So you should include in your LUT any relevant combinations of buffer setting, PGA gain, and data rate you intend to use in your system

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 30 points

    Hi Bryan,

    Thank you for the final confirmation.

    It is clear now that while the MUX is irrelevant, using a Look-Up Table is indeed essential to correctly handle the various Buffer, PGA, and Data Rate combinations dynamically without latency.

    I have all the information I need to proceed. You may close this thread.

    Best regards and thank you again, Alessandro