Part Number: AFE5818
What is SPI mode (CPOL/CPHA)?
The SPI timing diagram shown appears to start SCLK with the idle signal high (CPOL=1).
I believe this is the source of the misunderstanding.
Now that I look closer, when the SCLK signal immediately after SEN=ON has a rising leading/first edge, idle=Low level then CPOL=0.
So finaly, is "SPI mode 0 (CPOL=0, CPHA=0)" correct?
Regards,
Kamada
