• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 48 subscribers
  • Views 206 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC39RF12EVM: Unable to get the JESD link working between DAC39RF12EVM and ZCU111

Preethi Padmanabhan
Prodigy 10 points

Part Number: DAC39RF12EVM
Other Parts Discussed in Thread: TSW14J59EVM

Dear TI team,
I would like some help to bring up the JESD link running between DAC39RF12EVM and TI JESD IP.
I already tried to read up on existing related posts such as this DAC39RF10EVM: Unable to get JESD link up with TI JESD IP and ZCU102 example design - Data converters forum - Data converters - TI E2E support forums . However, I did not find any solution. Therefore, any help would be appreciated. 

Description: I used the reference design provided for ZCU102 and TI JESD IP and modified it for ZCU111. The reference design internally has a 64point sine wave which I am using to test the DAC in JESD mode. I configure the reference design to use in "TX only" mode. 

I am providing a 4GHz sampling clock to the EVM (instead of 10.24 GHz due to equipment capability) and 125MHz reference clock. ZCU111 is connected via FMC connector. 

I am configuring the DAC for JMODE1, real data, 1 channel, 16b, 8 lanes, 8b10b encoding in subclass1 operation. SYSREF K factor = 32. I have also verified that LMFS parameters match (8-1-2-8). I use the DAC EVM GUI to configure the LMK, DAC and the clocks. 
After configuring the DAC via the EVM GUI and programming the FPGA, I am able to get the SERDES PLLs locked, SYSREF align statuses are also green on the GUI. I also noticed that DAC SYNCN (out from the DAC) goes high on the ILA on the FPGA side. However, JESD link and 8b/10b SYNC statuses are still "red" and I am unable to get the link working.

I would appreciate any useful help or directions to help me debug the JESD link.  
image.png


Also, I would like to request, if possible, the FPGA reference design used on TSW14J59EVM  with DAC39RF12EVM to test the DAC in JESD mode. This could also be a useful starting point. Regardless, appreciate any useful hints/directions for debugging further. Many thanks.

  • 0
    TI__Expert 4010 points

    Hey Preethi, 

    One thing to note is your reference clock should be 125MHz and not 160MHz (as indicated by the GUI). The device is acknowledging it is aligned to SYSREF which means it sees a sysref and its able to align itself. It has nothing to do with the JESD link itself however. 

    Also note that for subclass 1 you may need to set the RBD (elastic buffer release delay). If the elastic buffer overflow flag goes red you will want to look at your lane arrivals times (by pressing setup RBD). If you do that now the GUI will likely indicate that lane arrival ready is not set as the FPGA is getting the wrong reference clock. 

    Also you can try doing a subclass 0 link first to confirm all the rates are correct before you go for a subclass 1 link.

    Give that a try and let me know if that works.  

    Regards, 

    Matt

  • 0 in reply to Matthew Kramer
    Prodigy 10 points

    Hi Matt,

    Thank you for your suggestions. 
    I did try with 125 MHz and no luck yet. 
    I also tried subclass 0. I have physically probed and verified the different clocks on the scope. They seem OK. 

    I also tried lower lane rates etc. Still no luck. 

    I am planning to monitor some other signals on the FPGA side on the logic analyzer. 
    Would you have any hints on the TI reference design I mentioned? 

    Also, I would like to request, if possible, the FPGA reference design used on TSW14J59EVM  with DAC39RF12EVM to test the DAC in JESD mode. This could also be a useful starting point.

    Many thanks.