ADC3662EVM: LVDS issue

Additinal info:

today i do some experiments with the register 0x0E and REFBUF pin.

1. Before power up i put jumper J13 REFBUF=AVDD

2. Then power up and setup registers -> the signals are better but still not OK

3. I switched jumper J13 from REFBUF=AVDD to REFBUF=GND and waveforms starts to look OK.

I attach 3x3 images for all three cases(1st FCLK, 2nd DCLK, 3rd DA0)

1) With REFBUF=AVDD

2) After registers setup

3) After switch REFBUF from AVDD to GND

Hi Renan,

Can you please send us the EVM revision you are working with?

Also, can you please send us a picture of the EVM?

Next, please send us a detailed block diagram of your test setup?

All of this information will help us understand better with all the modifications that have been performed on the ADC3662EVM.

Regards,

Rob

Hi Rob,

Here is the ADC3662EVM Rev. E board connected to the TrenzElektronik FPGA board:

Modifications of the ADC3662EVM mentioned above.

The FPGA_CLK(sample clock 10MHz) and DCLKIN_FPGA(80MHz) are generated by one PLL = phase locked(but i noticed that P and N of the DCLKIN_FPGA clock are swapped on the ADC3662EVM -> inverted)

The connection between ADC3662EVM via FMC to the FPGA (1,8V Vcco bank), used 5V external power supply for the ADC3662EVM:

High speed interface:

outputs FCLK_P/N(FMC E2/3) connected to the FPGA inputs differentially as SUB_LVDS

outputs DCLK_P/N(FMC F4/5) connected to the FPGA inputs differentially as SUB_LVDS

outputs DA0_P/N(FMC E12/13) connected to the FPGA inputs differentially as SUB_LVDS

inputs DCLKIN_FPGA_N/P(FMC K16/17) connected to the FPGA outputs differentially as SUB_LVDS(I noticed, that the P and N are swapped on ADC3662EVM board, per FMC standard has connected to the K16 positive signal HA17_P_CC and on K17 negative signal HA17_N_CC - is it correct or should i invert/shift phase of clock by 180°in the FPGA to eliminate this swap?)

input FPGA_CLK(FMC H4) connected to the FPGA output single ended LVCMOS18

Serial configuration interface:

input(HW modifications: mount R133, unmount R139 and U19) SEN_FPGA(FMC G28) connected to the FPGA output single ended LVCMOS18

input(HW modifications: mount R134, unmount R140) SCLK_FPGA(FMC G27) connected to the FPGA output single ended LVCMOS18

bidir(we modified HW: mount R137, unmount R144 and U18, connect PCB pads of U18 by wire 7 <->5, 8<->4 and 9<->3) SDIO_O_FPGA (FMC G30) connected to the FPGA bidir single ended LVCMOS18

Additionally i tried to switch to 2-wire at 10MSPS -> FPGA_CLK=10MHz and DCLKIN_FPGA=40MHz. It works with the switching REFBUF as previous and i am can see changes on the DA0 and DA1 when i touch the analog input A by the probe. In the registers i changed only 0x07=0x6C to 0x07=0x4B and 0x19=0x00 to 0x19=0x10.

Hi Petr,

There is a lot of infromation here, and you have made a lot of modifications to the EVM and are trying to test many things at once. In the future, I would recommend starting with the ADC EVM and the TI provided FPGA capture card to evaluate the ADC before moving to your own FPGA solution. This one-step-at-a-time procedure helps narrow down points of failure whenever you encounter issues. Now, you have introduced many points of failure into the system, and it will be very diffcult to narrow down the cause of the issue.

Let me clear up a few points of confusion:

1. Registers 0x20, 0x21, and 0x22 are 0 by default. This is an error in the datasheet. If you want to redback a register, read back register 0x10E. This is the device_id register, and you should see it return a value of 0x09 for the ADC3662.
2. You should not be changing the DCLK. For 1-wire, DDC Bypass, 16-bit, 10MSPS mode, you need a DCLK of 80MHz.
3. The sample clock is necesary to perform any SPI operations. So, if you are using a single ended sample clock, you need to ensure that you pull the REFBUF pin to GND, according to the below table:

From here, I would recommend the following:

1. Use the attached ADC3662EVM RevE schematic (ADC3x6xEVM_RevE_SCH.PDF) to mark up the changes you have made so that we can review.
2. Give us ONE specific ADC mode (number of wires, decimation mode, resolution, sample rate, etc.) that you would like to use and provide the register configuration you are using to program the ADC.
3. Exaplain what issue(s) you are running into with the above mode, and ask any necessary questions.

I appreciate that you provided us lots of details, however if you can help us by organizing your thoughts into the above 3 items, we'll be able to better assist you with your issue.

Best,

Luke Allen

Hi Luke,

I tried to read 0x10E and it returns 0x00 - the register 0x10E is not mentioned in the datasheet, the last register in the register space is 0x92.

I am attach the changes in the HW for the connection between our FPGA board and the ADC3662EVM:
Green = mounted parts, Red = unmounted parts

Also, we have to remove J4 and J6 due to mechanical confilct with the SFP cage.

I would like to use ADC for measure of the analog input channel A with 1-wire LVDS@16bit 10MSPS(10MHz sample clock CLK and 80MHz DCLKIN LVDS clock) without any DSP decimation, complex format etc.

The register settings is following:

Read_ADC_register(0x10E); // Read ID
Write_ADC_register(0x00, 0x01);
Delay(100000000);

Write_ADC_register(0x07, 0x6C);
Write_ADC_register(0x13, 0x01); // E-Fuse load
Delay(100000000);
Write_ADC_register(0x13, 0x00);
Write_ADC_register(0x0E, 0x0B);


Write_ADC_register(0x19, 0x00); // FCLK config
Write_ADC_register(0x1B, 0x88); // Set resolution
//Write_ADC_register(0x20, 0x00); // FCLK pattern
//Write_ADC_register(0x21, 0x0F); // FCLK pattern
//Write_ADC_register(0x22, 0x0F); // FCLK pattern


Write_ADC_register(0x24, 0x04);
Write_ADC_register(0x25, 0x00);

With this setting i am getting bad FCLK signal(oscillations before and after expected rising/falling edge), DA0_P/N in high-Z.

When i started to play with REFBUF (REFBUF=AVDD -> register init -> REFBUF=GND) it started to work with data on the DA0 lane.

Edit:

I made some experiments with the 1^st board: CLK=10MHz -> 10MSPS, DCLKIN=40MHz, 2-wire interface and 16bits. I started to experiment with the REFBUF=GND without any switching to the AVDD.

After power-up I discovered that everything is working fine(first picture) until I write into 0x0E=0x0B. After the write, the FCLK seems corrupted(second picture).

Yellow = FCLK_P before and after write

Green = not used

I successfully changed interface mode to the 10MSPS@bits 2-wire(CLK=10MHz, DCLKIN=40MHz) -> FCLK=5MHz, DCLK=40MHz and gather following expected waveforms (FCLK, DCLK, DA0 and the last one picture DA1):

Yellow = positive of LVDS pair

Green = negative of LVDS pair

Pink = P – N

I made some experiments with this register and setup REFBUF=GND:

0x0E=0x09      Works

0x0E=0x0B      Doesn’t work

0x0E=0x0D      Works

Regards,

Petr

Hi Petr,

You are correct, we did not include register 0x10E in the datasheet intentionally. If you are not able to read back a value from register 0x10E when the device is powered on and clocked, that would indicate an issue with your SPI readback.

Your register config looks fine. The only register wrties required for 1-wire, 16-bit, bypass, 10MSPS are the following:

write(0x0, 0x1)
write(0x7, 0x6c)
write(0x13, 0x1)
write(0x1b, 0x88)

The rest of the registers are 0x00 by default, and do not need to be written to.

Are you saying that you were able to get the correct FCLK when you connect REFBUF to GND AND write register 0x0E to 0x09 or 0x0D?

Best,

Luke Allen

Hi Luke,

i set the register 0x0E=0x09 and enabled ramp generator incremented by 16. Now it seems to work. Here is my setup of registers:

FCLK, DCLK, DA0, DA0 zoomed (end of ramp - transition from ~65535(65520) -> 0)

And here is the sampled and correctly bit aligned data. After every 4096 sample(red circle) is short jump in values - this is caused by internal sampling logic(write enable signal) in our FPGA. So, it is not an error.

Regards,

Petr

Hi Petr,

This is interesting, because as long as you have REFBUF pulled to GND, you should not have to program register 0x0E. Thank you for sahring, I will look into this.

Nevertheless, I'm glad you have things working now. Please let me know if you ahve any further questions.

Best,

Luke Allen