Part Number: DAC3283
Hi ,
We are using DAC3283 in dual sync mode and trying to do phase matching.
Our setup includes 4 DAC3283 devices operating at 800MHz, with an IF range of 65MHz to 75MHz.
We are performing 4× interpolation within the DAC. The data is generated using Xilinx DDS and transmitted via Xilinx high-speed SelectIO.
Some additional specifications include,
Input clock: 800MHz
OSTR (same source as clock): 25MHz
Frame: 25MHz
We have observed that the DAC output frequencies are correct, however, in a few power cycles, there is a 70 deg phase shift in the output data between DACs.
The two channels in a single DAC are in phase and
clocks and OSTR to multiple dacs are in phase.
What might be causing this behavior?
