AFE882H1: AFE882H1, Chip select query

ANURAG LOKHANDE

Part Number: AFE882H1

Hi,

For AFE882H1, when CS pin is pulled down, AFE chip do not respond. When used while SPI communication, AFE chip responds. What could be reason? Pull down value 10k resistor.

Regards, Anurag

6 months ago

0 Paul_Frost 6 months ago

TI__Guru 56903 points

Hi Anurag,

Can you clarify what you mean by "CS pin is pulled down"? Do you mean that you leave CS always connected LO and do not gate the SPI transaction with CS?

0 ANURAG LOKHANDE 6 months ago in reply to Paul_Frost

Intellectual 270 points

Hi,

yes, CS always connected LOW.

0 Paul_Frost 6 months ago in reply to ANURAG LOKHANDE

TI__Guru 56903 points

Hi Anurag,

The AFE882H1 requires a gated SPI frame. CS must have a rising edge to latch the data inputted on the frame.

Thanks,

Paul

0 ANURAG LOKHANDE 6 months ago in reply to Paul_Frost

Intellectual 270 points

Hi,

Thanks!

can you please give more info on gated SPI frame?

0 Paul_Frost 6 months ago in reply to ANURAG LOKHANDE

TI__Guru 56903 points

The AFE882H1 will not latch any SPI data until a rising edge of the CS line is detected. The device will latch the most recent 24 or 32 bits of data on the rising edge of the CS line. The device ignores all other data on CLK and SDI until CS is low again. So every frame of SPI data must be gated by the CS being low, but the CS line cannot stay low indefinitely.

0 ANURAG LOKHANDE 6 months ago in reply to Paul_Frost

Intellectual 270 points

Hi,

Thanks!

Why it is different from standard SPI where CS can be kept low (continuous) and communication can be established. Is there any specific reason for this?

0 Paul_Frost 6 months ago in reply to ANURAG LOKHANDE

TI__Guru 56903 points

This device features options for daisy-chaining and CRC checksums in the transactions. This means that the device must be informed when the frame is complete for it to latch without misinterpreting the data.

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AFE882H1: AFE882H1, Chip select query