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ADC12DJ2700: ADC12DJ2700 Reference Design Support and Reference Materials Request

Sivakumar Sivaram
Prodigy 10 points

Part Number: ADC12DJ2700
Other Parts Discussed in Thread: AFE7950

Hi TI ,

I am currently working on a system design that uses the ADC12DJ2700 high-speed ADC in combination with a Xilinx Kintex UltraScale FPGA (XCKU085-1FLVA1517I). I would appreciate your technical guidance on the suitability of this device combination and recommended design practices.

The key system-level ADC requirements are as follows:

  • Input Frequency Range: 0.8 GHz to 6 GHz

  • Number of RF Inputs: 4

  • Required Dynamic Range: 60 dB

  • Signal Types: Continuous Wave (CW) and pulsed signals

  • Instantaneous Bandwidth: 1 GHz

 

Based on these requirements, I would like your advice on the following points:

  1. Device Suitability
    Is the ADC12DJ2700 an appropriate choice for meeting the above performance requirements?

  2. FPGA Compatibility
    Is the Kintex UltraScale XCKU085-1FLVA1517I a recommended FPGA for interfacing with the ADC12DJ2700 (including JESD204B/C bandwidth, lane count, and processing margin)?

  3. Reference Designs and Documentation
    While reference designs are available for devices such as the AFE7950, we have not been able to locate equivalent reference designs for the ADC12DJ2700.
    Could you please share any existing reference designs, evaluation platforms, application notes, or relevant documentation for this device?

  4. Device Initialization and Configuration
    What is the recommended approach for ADC12DJ2700 device initialization and configuration when used with a custom FPGA platform based on the Kintex UltraScale family?

Please let us know of any additional application notes, design guidelines, or best practices that would be helpful for implementing this ADC–FPGA combination.

The same case I have already raised through the TI customer support center and the case number is CS3192547.

Thank you for your support. I look forward to your guidance.

 

Regards,
Sivakumar S

  • 0
    TI__Expert 6530 points

    Hi Sivakumar,

     The input frequency range is DC - 8GHz, the number of RF inputs is only 2. You would need two of these devices to achieve 4 analog inputs. The ADC is capable of sampling at 2.7 GHz in dual channel mode or 5.4 GHz in single channel mode. Which would equate to an ibw of 1.35 or 2.7 GHz. 

    I am not familiar with this fpga exactly, I would double check its number of lanes + capable lane rates. The ADC has 16 total serdes lanes supporting up to 12.8 gbps lane rate per lane.

    We do not have any out of the box JESD IPs for this device.

    For ADC configuration I would recommend using the ADC GUI on ti.com.

    Thanks

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 10 points

    Hi Eric,

    When I was going through TI-JESD204 IP supported products and hardware, the ADC12DJ2700 has been mentioned. 

    So, what should be the procedure to approach for TI-JESD204 IP parameter configuration ?

    As you have mentioned to use ADC GUI for ADC configuration, please provide required GUI for the same.

    Also, please recommend if there are any other options for ADC which supports the specification.

  • 0 in reply to Sivakumar Sivaram
    TI__Expert 6530 points

    Hi Sivakumar,

    There should be a user guide online for the TI-JESD204 FPGA IP that will detail how to configure the IP. I think to get access you must first submit a request on ti.com and get approval for the IP.

    The GUI is available on the evm page for the part. You can find it at this link https://www.ti.com/tool/ADC12DJ2700EVM

    For other adc recommendations you can look at the TI product page for high speed ADCs https://www.ti.com/product-category/data-converters/adcs/high-speed/overview.html

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 10 points

    Hi Eric,

    I got the EVM GUI. 

    I have query regarding the lane rate calculations.

    As per the datasheet https://www.ti.com/lit/ds/symlink/adc12dj2700.pdf , at page number 62 operating modes have been mentioned as shown in the below snapshot

    Lane rate = IQ sample rate * N * M *10/(8*L)

    We need JMODE3, our clock rate required is 2700MHz with decimation of x1. With these configuration if we do the Lane rate calculation 

    Lane rate = 2700MHz * 12 * 8 *10/(8*8) = 40500Mbps

    This is more than the supported lane rate which is 12.8 Gbps.

    So how we can derive lane rate within the supported value with clock rate 2700MHz and decimation of x1. For than can we change the value of M [no of converters. In the data sheet its mentioned as derived].

    Also, we have to use 16 lanes but in the data sheet table attached above it mentioned as 8 lanes. What does that means?

    Please support for the above queries.

    Thanks & regards,

    Sivakumar S  

  • 0 in reply to Sivakumar Sivaram
    TI__Expert 6530 points

    Hi Sivakumar,

    each jmode entry provides a serialization factor you can use to calculate the lane rate. This is parameter R in the table you show, R is defined as R = fbit/fclk. So to calculate the lane rate multiple R*Fs. So for JMODE3 at 2.7 GHz you would get a line rate of 2.7*2 = 5.4 Gbps.

    Thanks,

    Eric