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ADS7066: STM32H743 SPI Mode 0 issue reading ADS7066 registers

Part Number: ADS7066

Hello,

I am having an SPI communication issue between an STM32H743BIT (SPI master) and a TI ADS7066IRTER ADC using SPI Mode 0 (CPOL=0, CPHA=0).I write a configuration register and immediately read it back, but the read value does not match what was written. The logic analyzer shows correct MOSI data, but MISO often returns 0xFF or 0x80, and the SPI decoder reports “Settings mismatch”.

The write/read sequence is:

SPI_ADS7066_writeSingleRegister(hADS7066, GENERAL_CFG_ADDRESS, OPMODE_CFG_CLK_DIV_6);

if (SPI_ADS7066_readSingleRegister(hADS7066, GENERAL_CFG_ADDRESS) != OPMODE_CFG_CLK_DIV_6)
{
Throw(EMBL_ERROR);
}

Write and read functions used:

void SPI_ADS7066_writeSingleRegister(HANDLER hADS7066, uint8_t address, uint8_t data)
{
PSPI_ADS7066DESC pADS7066Desc = (PSPI_ADS7066DESC)hADS7066;
uint8_t dataTx[4] = {0};
uint8_t numberOfBytes = SPI_CRC_ENABLED(pADS7066Desc) ? 4 : 3;
EMBL_RETCODES ret;dataTx[0] = OPCODE_WREG;
dataTx[1] = address;
dataTx[2] = data;
if (SPI_CRC_ENABLED(pADS7066Desc))
dataTx[3] = SPI_ADS7066_calculateCRC(dataTx, 3, 0xFF);do {
ret = WRSPI_Transmit(pADS7066Desc->hSPI, dataTx, numberOfBytes);
} while (ret == EMBL_BUSY);
}uint8_t SPI_ADS7066_readSingleRegister(HANDLER hADS7066, uint8_t address)
{
PSPI_ADS7066DESC pADS7066Desc = (PSPI_ADS7066DESC)hADS7066;
uint8_t dataTx[4] = {0};
uint8_t dataRx[4] = {0};
EMBL_RETCODES ret;dataTx[0] = OPCODE_RREG;
dataTx[1] = address;
dataTx[2] = OPCODE_NULL;do {
ret = WRSPI_Transmit(pADS7066Desc->hSPI, dataTx, 3);
} while (ret == EMBL_BUSY);do {
ret = WRSPI_Receive(pADS7066Desc->hSPI, dataRx, 3);
} while (ret != EMBL_OK);return dataRx[0];
}

I attach some figures showing the clock signal taken with oscilloscope and all the signals taken with logic analyser.image (7).pngimage (2).pngimage (5).pngimage (3).png

  • Hello Guillermo, 

    Thank you for posting on TI's E2E forum!

    Could you please share an oscilloscope image containing the 4 digital lines? 

    From the image shared it appears that 1st clock might be offsetting the logic analyzer and causing the settings mismatch. 

    If this is the case then it would read the intended 0x080106, correct? 

    This 1st clock could also be affecting the ADS7066 command communication too, could you please make sure the timing requirements in Table 6.6 of the datasheet are being met? 

    The 0xFFFF that appears in that same frame is data from the ADC, if no register read command is given the ADC will output conversion data. Is full scale an expected output from the configured channel? 

    Just as a reminder, when reading back a value from a register the 1st frame should have the read command along with the address, then the register contents will be output in the following frame. 

    With that said, it does appear that the 2nd frame outputs 0x0, this could be because the previous frame was taken as a read register command instead. Another possible issue with the SCLK timing could be the width of the last SCLK, this duty cycle mismatch could possibly be causing the last bit to be lost further shifting the data in the spi command and causing other issues. Could the SCLK duty cycle kept uniform at least with the main 24 or 32 SCLK clocks? 

    Best regards, 

    Yolanda