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ADS127L21B: Adding ISO6041 (high speed digital isolator) to TIDA-01079 Low-Noise, Highly Linear, Analog Front-End Reference Design

Part Number: ADS127L21B
Other Parts Discussed in Thread: ISO6041, TIDA-010970, ADS127L21

e2e, 

I would like to add ISO6041 digital isolation between ADS127L21B digital output lines and the off board connector for the TIDA010970 Low-Noise, Highly Linear, Analog Front-End Reference Design. 

 

What are the key design considerations I need to keep in mind adding the digital isolator? 

 

How will adding a digital isolator to the ADS127L21B effect the test data in this report? 

 

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Thank you,

Adam

  • Hello Adam,

    Since the TIDA-010970 is focused on very low speed, low-bandwidth measurements, there will not be any noise degradation due to clock jitter.  The internal noise of the ADC will be much higher than than any jitter added noise at these low bandwidths.

    From a timing perspective, you will want to reduce the SCLK frequency to account for the added propagation delay of the isolator.  The ADC launches data on the rising SCLK edge, and the data capture board [Precision Host Interface (PHI)], captures the data on the falling edge.  The default digital supply used by this design is 2.5V, and according to the ISO6041 datasheet, the propagation delay will be 13.1ns max.  The ADS127L21 propagation delay from SCLK rising edge to valid data on SDO is 19ns.  Total round-trip maximum propagation delay will then be 2*13.1ns+19ns, or 45.2ns.  This will limit the theoretical maximum SCLK frequency to 11MHz (assuming a perfect 50% duty cycle), and accounting for other small delays, the maximum frequency should be 10MHz.

    You can easily adjust the SCLK frequency in the GUI used with this design.  Since the maximum data rate for this design is 60sps (1 NPLC), I recommend setting SCLK frequency to 3.2MHz, which will be equal to the system clock frequency.

    Regards,
    Keith Nicholas
    Precision ADC Applications