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ADS1274 SPI and McSBP

Manuel Fernandez-Ros
Intellectual 880 points
Other Parts Discussed in Thread: ADS1274, TMS320C6455

Hello

I'm working with DSK6455 + 5-6K interface + ADS1274 EVM boards. I'm using FS protocol and it works perfectly. Now I need to work with SPI protocol but I don't understand well how it works.

When S12 is on the left (SPI) the 27 MHz clock is connected to CLK signal (ADS1274) and J5.5 (CLKR) and DSP 6455 must generate the CLKX signal (SCLK) via McBSP. The base frequency is 200 MHz and I don't know how generate  a SCLK signal on CLKX pin from 200 MHz, because the frequency must be a rate of 1, 1/2, 1/4, ..... of 27 MHz.

Can you explain me how must I work with the SPI protocol.

Best regards.

Manuel.

  • 0
    TI__Guru**** 180741 points

    Hi Manuel,

    The SCLK used in SPI mode should (ideally) be a ratio of the main 27MHz clock to minimize system noise.  If you are not exactly at 1 or 1/2, 1/4...the ADS1274 will still work, you may see a little lower performance though. 

    You could set the CLKDIV bit in the McBSP registers to get close - say 25MHz - which will allow you to continue testing out your interface and software.  The setup of the 5-6K Interface Board and the ADS1274EVM should also allow you to provide an external clock sourced by your DSK6455.  The connector J5 (pin 17) should connect back through the 5-6K interface to one of the timer outputs of your TMS320C6455.  You could use that timer as a clock source and bypass the on-board 27MHz clock found on the EVM to get the correct ratio of clock to SCLK for best performance.

  • 0 in reply to Tom Hendrick
    Intellectual 880 points

    Hello Tom,

    Yes, you are right. I think that my problem is that I don't understand well the SPI compatible protocol. I don't understand why /DRDY is connected to FSR. I am trying to work similar to FS protocol, but perhpas this is the problem.

    I have been reading about SPI and /DRDY is not a neccesary signal. Then, what is the correct procedure?

    Perhaps:

    - Control /DRDY via polling or interrupts and then read data.

    or

    - /DRDY activates the reading via FSR. Does /DRDY synchronize McBSP?

    Sorry but my english is little.

    Best regards.

    Manuel Fernández

  • 0 in reply to Manuel Fernandez-Ros
    TI__Mastermind 43915 points

    Hi Manuel,

    I understand the confusion. The /DRDY line is not a part of the four wire SPI protocol which includes /CS, SCLK, Din, and Dout. It an additional bit which pulses when new data is ready and is meant to be used as an interrupt to begin SPI transmission. The ADS1274 has two selectable interfaces, a SPI compatible interface and a Frame Sync interface. The EVM was designed as apart of the EVM-PDK which includes software that was written in the Frame Sync mode to evaluate the part. You can read about the two communication options in the ADS1274 by looking through the data sheet. It sounds like you are interested in using a SPI compatible interface with the ADS1274, which is fine. The /DRDY line is used as an interrupt. You will notice that the ADC does not include a /CS line and just has SCLK, DIN and DOUT. Since this part does not have any internal registers, DIN is used for Daisy Chain mode only. Dout and SCLK are the two lines that you care about.

    Regards,

    Tony Calabria