Part Number: ADC12J4000EVM
Other Parts Discussed in Thread: ADC12J4000
Hello TI High Speed Data Converters Team,
I am a researcher in the Physics Department at The Hebrew University of Jerusalem. We are using the ADC12J4000EVM combined with the TSW14J56EVM for a LiDAR (photon detection) application.
The Challenge: Our application requires detecting sporadic, low-amplitude analog pulses. We need the TSW14J56 capture to be triggered only when the analog input signal crosses a specific threshold (Data-Dependent Triggering). Currently, the standard external trigger input (J13) requires a digital CMOS signal, but our source is analog. We want to avoid adding external hardware comparators to the signal path to maintain signal integrity.
Our Questions:
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Internal Trigger: Does the TSW14J56EVM (via HSDC Pro or current firmware) support a "Data-Dependent Trigger" or "Analog Level Trigger" mode where the FPGA monitors the data stream and triggers capture upon threshold crossing?
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ADC Hardware Features: Can we configure the ADC12J4000's Over-Range (OR) or Fast Detect output pins to act as a trigger source for the TSW14J56 when the signal exceeds a set limit?
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Custom Solution: If this feature is not supported by default, is it possible to obtain the TSW14J56 FPGA source code (Quartus project)? This would allow us to implement a digital comparator logic within the FPGA for our research needs.
We appreciate your guidance on the best method to achieve this self-triggered capture.
Best regards, Asaf
