Part Number: DDC2256A
Thats a screenshot form the DDC2256A datasheet page 32. As the register 0x3A is initialized with 0x00, it seems that the FCLK is normally a CMOS output (as in description 0: FCLK is CMOS signal). Is that correct? In the typical application it is a LVDS singal, which makes sense as DOUT and DCLK are as well.
So does this bit explicitely has to be set to have FCLK as a LVDS or is it somehow a typo?
