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ADC168M102R-SEP: Leaking channel 2 on 3 both adc A and B

jtw
Prodigy 40 points

Part Number: ADC168M102R-SEP

Hello TI Team

in the moment we face an issue when reading the ADC. It seems like when applying a external dc voltage we have a leakage between two channel which we cant observe when reading with the multimeter, so there both inputs to the adc seem fine.  

  • Config:
    • M0/1 = 0
    • Full Clock Mode
    • RD and CONVST tied together
    • CSn low during operation
    • ADC reference both on REFIO1, externally REFIO1 has a 22uf and close 100nF Cap.
    • CMx external is floating. <- we do a test in the moment with tying it to GND
    • Pseud differtial
    • Mux Channels 0,1 are grounded on both A and B
    • Mux Channels 2,3 are connected to a source in the moment 0.317V
  • Config regs:
    • CONFIG= 0x01C0, FULL CLOCK, PSEUDO
    • CONFIG Manual Switching order 0,1,2,3 = 0x00C0,0x40C0,0x80C0,0xC0C0
    • REFDAC1= 0x3C0 -> 2.35V
    • REFCM = 0xFF00

ISSUE:

So when we inject in one of the channels of 2,3 a Voltage we see that the other channel also gets a bit of energy and it misses on the other. i.e. channel 2 with 3V so we see at the input by reading with a multimeter it is exactly 3V when we read the ADCs we see in channel 2 is 2.9 and in channel 3 is 0.4.

In operation of the ADC i have one doubt:

In my config i have the READ and CONVST tied together. And as descirbed in the datasheet im having both asserted for 20 Clks in order to speed up the readout so we read before BUSY is low. 

Any thoughts what could lead to this behaviour?

 

Thanks and BR

 

  • 0
    Prodigy 40 points

    So looks after checking a bit further it seems the s+h is not fully discharged, we followed the recomanditions for the buffer in the datasheet. When sample two times the same input the second is ok. As we have Convst and read connnected we keep them for about 20 cycles. Is there a problem with the discharge?

  • 0 in reply to jtw
    TI__Expert 7960 points

    Hello JTW, 

    Welcome to TI's E2E forum! Thank you so much for the very detailed description of the system configuration, it is very much appreciated it. 

    The configuration shared is great by the way, I see no issue with that. Although I am curious on the test with shorting CMx to ground (REFCM = 0xFF00 sets the common mode to the internal REFIO1 and for ADC sampling purposes it is not in use), but that is not relevant to the current issue. 

    There is bound to be some channel to channel memory, especially when one channel is at a voltage>VREF/CM and the other close to GND, but at this range it is unusual. I would like to confirm it is not a timing issue.  

    Would you be able to share an oscilloscope or logic analyzer image of what the data transaction looks like when reading these two channels?

    What is the SCLK frequency? 

    Just to confirm here, does the full frame have 40 clocks?  Does the CONVST/RD go high at least 12ns before the 1st rising clock? 

    Could you try keeping CONVST/RD asserted for more than 20 clocks to make sure the RD falling edge isn't triggering too early and the ADC is outputting old data? 

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 40 points

    Hi Yolanda

    thanks for the quick reply

    i can provide some additional info, grounding didn't improve the situation. 

    The Setup time is kept ~14 ns, could be increased. We reduced for now the speed to 9MHz but want to achieve as high sampling rate as possible. We can keep the CONVST/RD for longer in fact i do it for 22 cycles which worsened the situation. 

    Sammling every channel twice did the trick, in fact i fear the settling time for the Mux switching is the problem.

    Few follow up questions:

    1. Mux switch setteling time?
    2. Exact point where the mux is switched?
    3. Shall we wait for Busy low until we read or is it possible to read a bit earlier?
    4. Since we have RD/CONVST on same signal there is a bit of a problem since CONVST is sampled on rising but SDI are on falling edge. Is the RD a asyncronous signal or is it sampled on a edge, in anyway what distance do RD and SDI need to have? Or is this covered when we can keep Ts1 and Th1 ? Is SDI sampled at the same time?

    BR

  • 0 in reply to jtw
    TI__Expert 7960 points

    Hello JTW,

    Could you please share a schematic, an oscilloscope or logic analyzer image of the digital communication, as well as what the raw data read looks for 1 channel in the 1st (with error) and 2nd read (correct)?

    Is the 2nd reading made right after the 1st read or is there a channel change in between? 

    What is being used to drive the ADC inputs? Was any simulation or calculation done to make sure that it could drive the ADC's sample and hold circuity? 

    The mux settling time is well within the acquisition time. 

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 40 points

    Hello Yelonda

    Yes basically we read one time with quite some energy from the previous and the second sample is ok no switch between both, than we switch. Ideally would be good to switch every time. What I saw is that it gets worse when i extend the const/rd high. So i assume the mux switch happens with the clocking in of the next read channel. So in order to maximize the sampling freq. with this double sampling we lose half of the rate. The Schema we cant share here.

    will provide some captures. We would like to switch every time. Can you please answer to the rest of the questions as this is not so clear from the DS:

    1. Mux switch settling time?
    2. Exact point where the mux is switched ?
    3. Shall we wait for Busy low until we read or is it possible to read a bit earlier?
    4. Since we have RD/CONVST on same signal there is a bit of a problem since CONVST is sampled on rising but SDI are on falling edge. Is the RD a asyncronous signal or is it sampled on a edge, in anyway what distance do RD and SDI need to have? Or is this covered when we can keep Ts1 and Th1 ? Is SDI sampled at the same time?

    BR

  • 0 in reply to jtw
    TI__Expert 7960 points

    Hello JTW,

    The mux switches after the 18th clock falling edge in half clock mode (or 24th rising edge in full clock mode). The switches delay is in the ns range and tD2 can be used as a conservative settling time delay. 

    In half-clock mode the conversion takes 17.5 clocks, the device then takes half a clock to pre-charge the internal capacitors, then the switches connect to the inputs for acquisition. 

    Busy does not need to be low to read the data, but RD timing is important to read correct data. 

    CONVST is sampled on the rising edge, while the RD is dependent on a falling edge.

    When both are tied together in full clock mode then the rising edge of the CONVST/RD is what designates the 1st clock. After CONVST transitions high, the following rising clock edge (with at least 12ns delay) will be the 1st clock. Then it would be waiting for the conversion to end, then bringing down CONVST/RD. 

    Could you please try again but delaying closer to 24/25 clocks?

     

    I am looking forward to the data communication captures. 

    Best regards, 

    Yolanda