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DAC8742H: Gap error, HART test

Oba
Mastermind 18065 points

Part Number: DAC8742H

Hello,


My customer has some questions for DAC8742H HART related things.

 

There is an item of “BACK Timing with STXs Errors” in HART conformance test.

The test machine sends STX(with Gap Errors) and the device has to detect the Gap Error and regulate to process it.

They try to read Gap signal from bit 12 of Modem Status register, but the Gap error is hard to read.

 

Then they have below 2 questions

1) From when to when does this Gap Error condition exist? Even if a Gap Error(bit12=1) occurs, receive operation continues.
So if the next byte is received, will the “1” state of bit12 be covered?

 

2) In the datasheet, there is not so many explanation for bit12 of Modem status register. Do you have any other literature which explained more detail?

Regards,
Oba

  • 0
    TI__Guru** 100885 points

    Oba-san,


    1. A gap error detects when there is too much time between HART character transmissions. If the gap error occurs, the device writes a 1 into bit 12 of the MODEM_STATUS register. The bits in the MODEM_STATUS register are "sticky". This means that when the error occurs and sets the bit, the user must clear the bit to reset the check. The error bit will continue to show the error until a 1 is written into the MODEM_STATUS register bit 12. If a gap error is detected, you need to check the MODEM_STATUS register and write a 1 into bit 12 before the end of the character to detect a gap error in the next transmission.

    2. In the DAC8742H gap error detection, the device checks the time between the stop bit and the next start bit for the HART communication into the device. If this time is greater than one HART character time (9.17ms), then the gap error is indicated.


    Joseph Wu

  • 0 in reply to Joseph Wu
    TI__Mastermind 18065 points

    Hello Joseph,

    They have an additional question for your reply to (1).

    From your answer, if receiving an arbitrary frame, at least a GapError will occur at the end of the frame. And bit-12 of the MODEM_STATUS should be read as "1". Is this understanding correct?

    For example, after the master sends "FF FF FF FF FF 82 A AB 01" and the device receives the last "01", "1" should be read from bit-12 of MPDEM_STATUS?

    If the above understanding is correct, if would be appreciated if you have any advice on the below behaviour.

    MCU configuration: SPI Mode, Enable FIFO level interrupt, FIFO Level=3, There is no other configuration.
    Behavior: Received data can be read (received universal command and the replay is OK).
    Bit 12 of the MODEM_STATUS can't be read. 

    Do you see any insufficient configuration they should set?

    Regards,
    Oba

  • 0 in reply to Oba
    TI__Guru** 100885 points

    Oba-san,

    I'll need to review this with one of the digital designers. I'm not too familiar with the exact details of the gap error detection, and the answer depends on exactly how the gap error is detected. 

    Joseph Wu

  • +1 in reply to Joseph Wu
    TI__Guru** 100885 points

    Oba-san,


    I don't see any issues with the configuration, but I would check that the IF_SEL is high to use SPI mode. If they are able to get the data from the FIFO, this should be fine.

    I did check with design and at the end of a HART communication, there should be a gap error when the HART frame finishes. The device detects when the carrier detect misses a signal for longer than a character time. At the end of communication, the carrier is not detected and the gap error should come up in about 9.17ms. After the gap error occurs, you would need to clear the error.

    If you are not seeing the gap error, then I would check a few things. First makes sure the device first detected the carrier, then check that the carrier is not detected. They should be able to see this with the CD in the MODEM_STATUS register in bit 1 (if SPI mode is used). After the HART signal is detected, I would poll the MODEM_STATUS register to check that CD goes to 1 to detect the signal and then returns to 0 after the signal completion. The CD flag is not sticky, so you do not need to write a 1 to clear it.

    After that, check MODEM_STATUS again for the GAP error. Again, it will take about 9.17ms after the CD returns to 0 to set a GAP error. Even it the MODEM_IRQ_MASK is set for GAP, it blocks the trigger for the IRQ, but it should still report the error in the MODEM STATUS register.


    Joseph Wu