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AFE5809: Clarification Required on ADC Clock Configuration for AFE5809 Ultrasound Prototype

Harsh Shirke
Prodigy 160 points

Part Number: AFE5809
Other Parts Discussed in Thread: CDCE72010, , LMK04821, LMK04826, CDCM7005, CDCM1802

Hello TI Team,

We are planning to use the AFE5809 for our ultrasound product development prototype.

We would like clarification regarding the ADC clock input configuration:

  1. For the ADC clock input, can we directly use an external clock generator or buffer?

  2. Is it recommended to use the CDCE72010 to drive the ADC clock?

  3. If the CDCE72010 is used to drive both the ADC clock and the CW clock simultaneously, are there any performance concerns or limitations we should be aware of?

  4. For the ADC clock, is it acceptable to use a 40 MHz oscillator similar to the one used on the AFE5809EVM, or would you recommend using a dedicated clock buffer/generator such as the CDCE72010?

We would appreciate your guidance on the recommended clocking architecture to ensure optimal performance.

Best regards,
Harsh Shirke

  • 0
    TI__Intellectual 1080 points

    Hi Harsh,

    1. Yes. For ADC clock, external clock or buffer can be used

    2. We generally recommend LMK04826/LMK04821 or CDCM7005 to drive the ADC clock. CDCE72010 can also be used if it is similar in performance with the clock buffers mentioned. 

    3. In CW mode, anyway ADC is not required. So ADC clock can be turned off.

    4. It depends on the application. If fixed sampling rate is used in application then 40MHz oscillator is enough. But for debug purposes, we generally recommend to have two paths for ADC clock. Just in case one clock path fails.  

  • 0 in reply to Sheetal Gupta
    Prodigy 160 points

    Hi Sheetal,

    Thank you for your clarification.

    We are designing an 8-channel ultrasound system, and the clock requirements for the front-end devices are as follows:

    1. AFE5809 (8-Channel ADC Front End)

    • Number of Devices: 1 (8 receive channels)

    • ADC Sampling Clock: 10 MHz to 65 MHz

    • Clock Input Type: LVDS differential preferred

    • Jitter Requirement: < 1 ps RMS (to maintain ADC SNR performance)

    • Phase Noise: Low close-in phase noise required for imaging quality

    2. TX08D (Transmit Section)

    • Clock Type: LVDS differential

    • Frequency: Up to 250 MHz (maximum)

    • Jitter Requirement: Low jitter for precise transmit timing alignment

    3. Cyclone 5E FPGA

    • System Clock: 50–100 MHz (flexible)

    • Reference Clock: Clean differential clock preferred for PLL stability

    • Jitter Requirement: Low jitter recommended for reliable LVDS data capture

    In AFE5809, We decided to use TGC mode and we are not going for a CW mode.

    Based on the above requirements, kindly recommend a suitable clock tree architecture for this 8-channel ultrasound system.

    Best regards,
    Harsh Shirke

  • 0 in reply to Harsh Shirke
    TI__Intellectual 1080 points

    Hi Harsh,

    We would recommend you to use LMK04826. This device is SPI programmable to use as clock buffer or clock divider with good jitter performance. 

  • 0 in reply to Sheetal Gupta
    Prodigy 160 points

    Hi Sheetal,

    Based on our discussion, my understanding is that we can use the LMK04826 as the primary clock solution for our design.

    Kindly confirm the following:

    • We do not require an external programmable oscillator as a master clock reference for the LMK04826.

    • We do not require an additional external clock buffer after the LMK04826 for distribution.

    Please confirm if this understanding is correct, or advise if any additional components are recommended for optimal performance.

  • +1 in reply to Harsh Shirke
    TI__Intellectual 1080 points

    Hi Harsh,

    1. LMK04826 needs a reference clock which can be generated from an external oscillator. Oscillator can provide fixed clock (doesn't have to be programmable, recommended: VCC1-B3B-125M0000). 

    2.  Generally for high frequency (60MHz-80MHz), LMK04826 will be able to generate the divided clock output but for low frequency, it has a limit on the clock division factor. So, we put one more clock buffer/divider (CDCM1802) at the output of LMK04826 to get the low frequency clock. But this limitation is not there if you use LMK04821. In LMK04821, you have extra programmability for higher division factors and hence can get 10MHz-80MHz easily without using any extra clock buffers at the output of LMK04821. 

    So in summary, LMK needs a reference clock at its input which can be generated from external oscillator. And since you want to support low frequency from LMK, it's better to use LMK04821. If you use LMK04821, then no external clock buffer is needed. However if you choose LMK04826, you have to put extra external clock buffer. Performance wise, both LMKs are similar. 

  • 0 in reply to Sheetal Gupta
    Prodigy 160 points

    Hi Sheetal,

    Thank you very much for your support and valuable suggestions.

    I truly appreciate your guidance and timely assistance throughout the process.